3D semiconductor memory device including floating gate and method of manufacturing the same
Provided herein may be a semiconductor device and a method of manufacturing the same. The semiconductor device may include a gate stacked structure including a plurality of insulating layers and a plurality of conductive layers that are alternately stacked, a vertical structure extending into the gate stacked structure, a floating gate disposed between the vertical structure and the plurality of conductive layers, and a dielectric pattern disposed between the floating gate and the plurality of conductive layers. The floating gate may include a first portion that is adjacent to the vertical structure and a second portion that is adjacent to the dielectric pattern, and the dielectric pattern may contact an upper surface, a lower surface, and a sidewall of the second portion.
1 . A semiconductor device, comprising:
a gate stacked structure including a plurality of insulating layers and a plurality of conductive layers that are alternately stacked;
a vertical structure extending into the gate stacked structure;
a floating gate disposed between the vertical structure and the plurality of conductive layers; and
a dielectric pattern disposed between the floating gate and the plurality of conductive layers,
wherein the floating gate comprises a first portion that is adjacent to the vertical structure and a second portion that is adjacent to the dielectric pattern,
wherein the dielectric pattern does not contact an upper surface and a lower surface of the first portion, and
wherein the dielectric pattern contacts an upper surface, a lower surface, and a sidewall of the second portion.
2 . The semiconductor device according to claim 1 , wherein a vertical length of the first portion is longer than that of the second portion.
3 . The semiconductor device according to claim 1 , wherein the dielectric pattern comprises:
a first high dielectric layer formed along the upper surface, the lower surface, and the sidewall of the second portion;
a second high dielectric layer formed along an upper surface, a lower surface, and a sidewall of each of the plurality of conductive layers; and
a low dielectric layer disposed between the first high dielectric layer and the second high dielectric layer.
4 . The semiconductor device according to claim 3 , wherein the plurality of insulating layers protrude farther toward the vertical structure than the plurality of conductive layers.
5 . The semiconductor device according to claim 4 , further comprising:
a plurality of insulating patterns disposed between the plurality of insulating layers and the vertical structure.
6 . The semiconductor device according to claim 5 , wherein the first portion is disposed in a space between the plurality of insulating layers, and
wherein the second portion is disposed in a space between the plurality of insulating patterns.
7 . The semiconductor device according to claim 5 , wherein the first high dielectric layer and the second high dielectric layer extend to a space between the plurality of insulating patterns and the plurality of insulating layers.