Semiconductor device and electronic system including the same
A semiconductor device includes a substrate extending in a first direction and a second direction perpendicular to the first direction, the substrate disposed on a peripheral circuit region and has a cell array region formed therein, a first mold structure which includes insulating layers and gate electrode layers alternately stacked on the substrate, first and second channel structures penetrating, in a third direction perpendicular to the first direction and the second direction, the first mold structure and spaced apart from each other in the first direction, a separation structure penetrating the first mold structure in the third direction between the first and second channel structures and separating the gate electrode layers in the first direction, and first and second auxiliary channel structures penetrating a part of the first mold structure between the separation structure and the first channel structure, and between the separation structure and the second channel structure.
1 . A semiconductor device comprising:
a substrate extending in a first direction and a second direction perpendicular to the first direction, the substrate disposed on a peripheral circuit region and having a cell array region formed therein;
a first mold structure which includes insulating layers and gate electrodes alternately stacked on the substrate;
first and second channel structures penetrating, in a third direction perpendicular to the first direction and the second direction, the first mold structure and spaced apart from each other in the first direction;
a separation structure penetrating the first mold structure in the third direction between the first and second channel structures and separating the gate electrodes in the first direction, the separation structure formed of an insulating material; and
first and second auxiliary channel structures between the separation structure and the first channel structure, and between the separation structure and the second channel structure, respectively,
wherein the first and second auxiliary channel structures contact a set of the gate electrodes.
2 . The semiconductor device of claim 1 , further comprising:
a common source plate disposed on the substrate below the gate electrodes and in contact with the first and second channel structures,
wherein the first and second auxiliary channel structures penetrate an upper part of the first mold structure and are not in contact with the common source plate.
3 . The semiconductor device of claim 1 , wherein heights of lower ends of the first and second auxiliary channel structures are higher than heights of lower ends of the first and second channel structures.
4 . The semiconductor device of claim 1 , further comprising:
a second mold structure which includes insulating layers and gate electrodes alternately stacked on the first mold structure,
wherein the first and second auxiliary channel structures penetrate the second mold structure.
5 . The semiconductor device of claim 1 , wherein the first and second channel structures are disposed in first and second channel holes each include a blocking film, a charge storage film, a tunnel insulating film, and a semiconductor pattern formed along profiles of first and second channel holes penetrating the first mold structure,
the first and second auxiliary channel structures each include an oxide layer formed along profiles of first and second auxiliary channel holes which penetrate a part of the first mold structure, and
diameters of the first and second auxiliary channel holes are smaller than diameters of the first and second channel holes.
6 . The semiconductor device of claim 1 , wherein:
the first channel structure includes first and second channel patterns which are spaced apart from each other in the second direction,
the second channel structure includes third and fourth channel patterns spaced apart from each other in the second direction,
the separation structure includes first and second separation patterns spaced apart from each other in the second direction between the first and second channel structures, and
the first and second auxiliary channel structures include a first auxiliary channel pattern disposed between the first channel pattern and the first separation pattern in the first direction, and a second auxiliary channel pattern that is spaced apart from the first auxiliary channel pattern in the second direction and disposed between the second channel pattern and the second separation pattern in the first direction.
7 . The semiconductor device of claim 6 , wherein the first and second separation patterns are merged with each other to form a bar-shaped first extension pattern that extends in the second direction, and a first protrusion pattern that protrudes from the first extension pattern in the first direction.
8 . The semiconductor device of claim 7 , wherein the first and second auxiliary channel patterns and the first and second separation patterns are merged with each other to form a second protrusion pattern that protrudes in the first direction.
9 . The semiconductor device of claim 6 , wherein each of a first distance between the first auxiliary channel pattern and the second auxiliary channel pattern, a second distance between the first auxiliary channel pattern and the first channel pattern, and a third distance between the first auxiliary channel pattern and the first separation pattern is 0.5 times or more and 1.5 times or less than a distance between the first channel pattern and the second channel pattern.
10 . The semiconductor device of claim 6 , wherein each of a first distance between the first auxiliary channel pattern and the second auxiliary channel pattern, a second distance between the first auxiliary channel pattern and the first channel pattern, and a third distance between the first auxiliary channel pattern and the first separation pattern is 0.5 times or more and 1.5 times or less than a distance between the first separation pattern and the second separation pattern.
11 . The semiconductor device of claim 6 , wherein the first channel pattern and the first separation pattern overlap each other in the first direction, and the second channel pattern and the second separation pattern overlap each other in the first direction,
a center of the first auxiliary channel pattern does not overlap a center of the first channel pattern and a center of the second channel pattern in the first direction, and
the center of the first auxiliary channel pattern does not overlap a center of the first separation pattern and a center of the second separation pattern in the first direction.
12 . A semiconductor device comprising:
a substrate, extending in a first direction and a second direction perpendicular to the first direction, on which a plurality of cell regions, a separation region between two adjacent cell regions of the plurality of cell regions, and a dummy region between one of the plurality of cell regions and the separation region are formed;
a mold structure which includes insulating layers and gate electrodes alternately stacked on the substrate;
first and second channel structures penetrating, in a third direction perpendicular to the first direction and the second direction, the mold structure and spaced apart from each other in the first direction, in each of the plurality of cell regions;
a separation structure penetrating the mold structure in the third direction between the first and second channel structures, in the separation region; and
first and second auxiliary channel structures which are spaced apart from each other in the second direction, in the dummy region, wherein:
the separation structure contacts a set of the gate electrodes,
the first and second channel structures each include a blocking film, a charge storage film, a tunnel insulating film, and a semiconductor pattern which are formed along profiles of first and second channel holes penetrating the mold structure,
the first and second auxiliary channel structures each include an oxide layer formed along profiles of first and second auxiliary channel holes that penetrate a part of the mold structure, and
at a first height above a surface of the substrate, maximum diameters of the first and second auxiliary channel holes are smaller than maximum diameters of the first and second channel holes.
13 . The semiconductor device of claim 12 , wherein the separation structure overlaps the first channel structure in the first direction.
14 . The semiconductor device of claim 12 , wherein the first and second auxiliary channel structures penetrate an upper part of the mold structure and do not come into contact with a bottom surface of the mold structure.
15 . The semiconductor device of claim 12 , wherein the first and second channel structures each have a circular cross-sectional shape as viewed from a plan view, and the first and second auxiliary channel structures each have a circular cross-sectional shape as viewed from a plan view.
16 . The semiconductor device of claim 12 , wherein the first and second auxiliary channel structures and the separation structure are merged with each other to form first and second protrusion patterns protruding in the first direction, and
a first length of the first protrusion pattern protruding in the first direction is different from a second length of the second protrusion pattern protruding in the first direction.
17 . An electronic system comprising:
a main board;
a semiconductor device on the main board; and
a controller electrically connected to the semiconductor device on the main board,
wherein the semiconductor device includes
a substrate, extending in a first direction and a second direction perpendicular to the first direction, on which a plurality of cell regions spaced apart from each other in the first direction, a separation region disposed between two adjacent cell regions of the plurality of cell regions in the first direction, and a dummy region disposed between one of the plurality of cell regions and the separation region in the first direction are formed;
a first mold structure which includes insulating layers and gate electrodes alternately stacked on the substrate;
first and second channel structures that penetrate, in a third direction perpendicular to the first direction and the second direction, the first mold structure and are spaced apart from each other in the second direction, in each of the plurality of cell regions;
first and second separation structures disposed in the separation region, the first and second separation structures spaced apart from each other in the second direction; and
first and second auxiliary channel structures which are spaced apart from each other in the second direction in the dummy region,
wherein the first and second auxiliary channel structures penetrate an upper part of the first mold structure, and do not come into contact with a bottom surface of the first mold structure, and
wherein the first and second auxiliary channel structures contact a set of the gate electrodes.
18 . The electronic system of claim 17 , wherein each of the first channel structure and the first separation structure does not overlap centers of the first and second auxiliary channel structures in the second direction.
19 . The electronic system of claim 17 , wherein the first and second auxiliary channel structures and the first and second separation structures are merged with each other to form first and second protrusion patterns protruding in the first direction, and
a first length of the first protrusion pattern protruding in the first direction is different from a second length of the second protrusion pattern protruding in the first direction.
20 . The electronic system of claim 17 , further comprising:
a second mold structure which includes insulating layers and gate electrodes alternately stacked on the first mold structure,
wherein the first and second auxiliary channel structures penetrate the second mold structure.