Memory device and method of fabricating the same
A method of fabricating a memory device at least includes the following steps. A first stack structure is formed above a substrate. The first stack structure includes a plurality of first insulating layers and a plurality of first conductive layers alternately stacked. A top layer of the first stack structure includes a plurality of anti-oxidation atoms therein. A second stack structure is formed on the first stack structure. The second stack structure includes a plurality of second insulating layers and a plurality of middle layers alternately stacked. A slit trench is formed to extend from the second stack structure to a top first conductor layer of the plurality of first conductor layers. A protective layer is formed on a sidewall of the top first conductive layer exposed by the slit trench. The memory device may be a 3D NAND flash memory with high capacity and high performance.
1 . A method of fabricating a memory device, comprising:
forming a first stack structure above a substrate, wherein the first stack structure comprises a plurality of first insulating layers and a plurality of first conductive layers alternately stacked, and a top layer of the first stack structure includes a plurality of anti-oxidation atoms therein, the top layer is a portion of a top first conductive layer of the plurality of first conductive layers, and the plurality of anti-oxidation atoms are formed by performing a surface treatment process on the top first conductive layer;
forming a second stack structure on the first stack structure, wherein the second stack structure comprises a plurality of second insulating layers and a plurality of middle layers alternately stacked;
forming a slit trench, the slit trench extending from the second stack structure to the top first conductive layer; and
forming a protective layer on a sidewall of the top first conductive layer exposed by the slit trench.
2 . The method of claim 1 , wherein the plurality of anti-oxidation atoms comprises nitrogen atoms.
3 . The method of claim 1 , wherein the surface treatment process comprises a plasma treatment process.
4 . The method of claim 3 , wherein a gas used in the plasma treatment process comprises ammonia, nitrogen or a combination thereof.
5 . The method of claim 1 , wherein forming the protective layer comprises performing a thermal oxidation process on the sidewall of the top first conductive layer exposed by the slit trench.
6 . The method of claim 1 , further comprising:
replacing a portion of the plurality of first insulating layers and a middle conductive layer of the plurality of first conductive layers with a second conductive layer; and
replacing the plurality of middle layers with a plurality of third conductive layers.
7 . A memory device, comprising:
a stop structure above a substrate;
a stack structure on the stop structure, wherein the stack structure comprises a plurality of insulating layers and a plurality of conductive layers alternately stacked; and
a slit, extending through the stack structure and a portion of the stop structure,
wherein the stop structure comprises a top layer, the top layer includes a plurality of anti-oxidation atoms therein, the top layer comprises a first semiconductor layer, and the plurality of anti-oxidation atoms are distributed in a top portion of the first semiconductor layer.
8 . The memory device of claim 7 , wherein the slit comprises a protective layer and a filling layer, and the protective layer is disposed between the stop structure and the filling layer.
9 . The memory device of claim 8 , wherein the plurality of anti-oxidation atoms are different from constituent elements of the protective layer.
10 . The memory device of claim 7 , wherein the plurality of anti-oxidation atoms comprise nitrogen atoms, and the protective layer comprises silicon oxide.
11 . The memory device of claim 10 , wherein a concentration of the nitrogen atoms ranges from 15 atomic % to 25 atomic %.
12 . The memory device of claim 7 , wherein a distribution range of the plurality of anti-oxidation atoms in the top portion of the first semiconductor layer is higher than a distribution range of the plurality of anti-oxidation atoms at a bottom surface of the slit.
13 . The memory device of claim 1 , wherein the stop structure comprises a middle layer disposed below the top layer and the slit, and the middle layer comprises a second semiconductor layer electrically connected to the slit.
14 . The memory device of claim 13 , wherein a sidewall of the first semiconductor layer and a top surface of the second semiconductor layer are covered by the protective layer.
15 . The memory device of claim 14 , wherein a concentration of the plurality of anti-oxidation atoms in the first semiconductor layer is larger than a concentration of the plurality of anti-oxidation atoms in the second semiconductor layer.
16 . The memory device of claim 14 , wherein the stop structure comprises a bottom layer below the middle layer, the bottom layer comprises a third semiconductor layer, and the third semiconductor layer does not have the plurality of anti-oxidation atoms.
17 . The memory device of claim 7 , wherein the top layer comprises silicon nitride.