Semiconductor device including a plurality of dielectric layers stacked on ferroelectric layer

1 . A semiconductor device comprising;

a first electrode;

a ferroelectric layer disposed on the first electrode that implements a negative capacitance;

a dielectric structure disposed on the ferroelectric layer, the dielectric structure including a first dielectric layer and a second dielectric layer; and

a second electrode disposed on the dielectric structure,

wherein the ferroelectric layer and the dielectric structure are electrically connected in series to each other,

wherein the ferroelectric layer and the dielectric structure together have a non-ferroelectric property, and

wherein the first dielectric layer and the second dielectric layer are alternatively stacked in the dielectric structure.

2 . The semiconductor device of claim 1 ,

wherein the dielectric structure comprises a plurality of unit stacks, and

wherein each of the plurality of unit stacks comprises one layer of the first dielectric layer and one layer of the second dielectric layer.

3 . The semiconductor device of claim 2 , wherein the dielectric structure further comprises inner barrier layers disposed between the plurality of unit stacks.

4 . The semiconductor device of claim 1 , wherein each of the first dielectric layer and the second dielectric layer is an epi-growth layer.

5 . The semiconductor device of claim 1 , wherein each of the first dielectric layer and the second dielectric layer has a thickness of 5 angstroms (Å) to 20 angstroms (Å).

6 . The semiconductor device of claim 1 , wherein one of the first dielectric layer and the second dielectric layer comprises hafnium oxide, and the other of the first dielectric layer and the second dielectric layer comprises zirconium oxide.

7 . The semiconductor device of claim 1 , wherein the ferroelectric layer comprises at least one of hafnium oxide and zirconium oxide.

8 . The semiconductor device of claim 1 , wherein the ferroelectric layer comprises at least one of doped hafnium oxide and doped hafnium zirconium oxide, and

wherein the doped hafnium oxide and the doped hafnium zirconium oxide comprises at least one dopant selected from carbon (C), silicon (Si), magnesium (Mg), aluminum (Al), yttrium (Y), nitrogen (N), germanium (Ge), tin (Sn), strontium (Sr), lead (Pb), calcium (Ca), barium (Ba), titanium (Ti), zirconium (Zr), gadolinium (Gd), and lanthanum (La).

9 . The semiconductor device of claim 1 , wherein the ferroelectric layer has a thickness of 1 nanometer (nm) to 4 nanometers (nm), and

wherein the dielectric structure has a thickness of 1 nanometer (nm) to 4 nanometers (nm).

10 . The semiconductor device of claim 1 , wherein each of the first electrode and the second electrode comprises at least one selected from gold (Au), silver (Ag), tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, and ruthenium oxide.

11 . The semiconductor device of claim 1 , further comprising a first barrier insulation layer disposed between the ferroelectric layer and the dielectric structure.

12 . The semiconductor device of claim 11 , wherein the first barrier insulation layer comprises at least one selected from aluminum oxide, yttrium oxide, and magnesium oxide.

13 . The semiconductor device of claim 11 , further comprising a second barrier insulation layer disposed between the dielectric structure and the second electrode.

14 . The semiconductor device of claim 11 , further comprising a reduction sacrificial layer disposed between the dielectric structure and the second electrode.

15 . The semiconductor device of claim 14 , wherein the reduction sacrificial layer comprises niobium oxide or titanium oxide.

16 . The semiconductor device of claim 11 , further comprising a crystallization seed layer, disposed between the first electrode and the ferroelectric layer, that induces crystallization of the ferroelectric layer.

17 . The semiconductor device of claim 16 , wherein the crystallization seed layer comprises magnesium oxide or zirconium oxide.

18 . The semiconductor device of claim 16 , further comprising a second barrier insulation layer disposed between the crystallization seed layer and the first electrode layer.

19 . The semiconductor device of claim 1 , wherein the ferroelectric layer comprises:

a first sub ferroelectric layer;

an inner barrier layer disposed on the first sub ferroelectric layer; and

a second sub ferroelectric layer disposed on the inner barrier layer.

20 . A semiconductor device comprising:

a first electrode;

a ferroelectric layer disposed on the first electrode that implements a negative capacitance;

a dielectric structure disposed on the ferroelectric layer and having a superlattice structure; and

a second electrode disposed on the dielectric structure

wherein the dielectric structure comprises a plurality of first paraelectric layers and a plurality of second paraelectric layers that are alternately stacked.

21 . The semiconductor device of claim 20 , wherein each of the plurality of first paraelectric layers and the plurality of second paraelectric layers is an epi-growth layer.

22 . The semiconductor device of claim 20 , wherein each of the plurality of first paraelectric layers and the plurality of second paraelectric layers has a thickness of 5 angstroms (Å) to 20 angstroms (Å).

23 . The semiconductor device of claim 20 , wherein the ferroelectric layer has a thickness of 1 nanometer (nm) to 4 nanometers (nm), and

wherein the dielectric structure has a thickness of 1 nanometer (nm) to 4 nanometers (nm).