Three dimensional semiconductor device stack, system having the same, and method of operating three dimensional semiconductor device stack

1 . A three dimensional semiconductor device stack comprising:

a first non-volatile memory array device comprising a plurality of planes;

a second non-volatile memory array device comprising a plurality of planes; and

a functional device electrically connecting to the first non-volatile memory array device and the second non-volatile memory array device, wherein the functional device comprises:

a z-direction switch configured to select one of the first non-volatile memory array device and the second non-volatile memory array device;

at least one bias voltage generator, at least one register, at least one automaton, and at least one buffer connected to the z-direction switch; and

a plane switch configured to select one of the planes of the selected first non-volatile memory array device or to select one of the planes of the selected second non-volatile memory array device.

2 . The three dimensional semiconductor device stack of claim 1 , wherein the functional device is disposed between the first non-volatile memory array device and the second non-volatile memory array device.

3 . The three dimensional semiconductor device stack of claim 2 , wherein a layout of the first non-volatile memory array device is symmetric to a layout of the second non-volatile memory array device.

4 . The three dimensional semiconductor device stack of claim 1 , wherein the functional device is disposed above the first non-volatile memory array device and the second non-volatile memory array device.

5 . The three dimensional semiconductor device stack of claim 4 , wherein each of the first non-volatile memory array device and the second non-volatile memory array device comprises:

a layer stack comprising a plurality of conductive layers and a plurality of insulating layers alternately arranged, wherein lengths of the conductive layers and the underlying insulating layers are sequentially decrease from bottom to top;

a plurality of vertical channel structures disposed in an array region of the layer stack; and

a plurality of contacts disposed in a stair case region of the layer stack and connected to the conductive layers.

6 . The three dimensional semiconductor device stack of claim 5 , wherein each of the first non-volatile memory array device and the second non-volatile memory array device comprises:

a first connecting layer; and

a second connecting layer disposed opposite to the first connecting layer and comprising a plurality of bonding pads bonded to the vertical channel structures and the contacts, respectively.

7 . The three dimensional semiconductor device stack of claim 6 , wherein the first connecting layer of the first non-volatile memory array device comprises a plurality of power rails, and the first connecting layer of the second non-volatile memory array device comprises a plurality of signal pads.

8 . The three dimensional semiconductor device stack of claim 7 , wherein a size of the power rails is greater than a size of the signal pads.

9 . The three dimensional semiconductor device stack of claim 5 , wherein each of the vertical channel structures comprises:

a storage layer;

an isolation pillar;

a channel layer disposed between the storage layer and the isolation pillar; and

a conductive plug disposed on the isolation pillar and in contact with the channel layer.

10 . The three dimensional semiconductor device stack of claim 1 , wherein the functional device is a non-volatile memory peripheral device, a processor device, a memory device, or a peripheral circuit and data processor device.

11 . The three dimensional semiconductor device stack of claim 1 , wherein the first non-volatile memory array device, the second non-volatile memory array device, and the functional device comprise wafers, chips, or combinations thereof.

12 . The three dimensional semiconductor device stack of claim 1 , further comprising an additional functional device disposed between or above the first non-volatile memory array device and the second non-volatile memory array device.

13 . A system having three dimensional semiconductor device stacks, the system comprising:

a substrate, wherein the substrate is an interposer substrate or a package substrate;

a plurality of three dimensional semiconductor device stacks disposed on the substrate, wherein each of the plurality of three dimensional semiconductor device stacks comprises:

a first non-volatile memory array device comprising a plurality of planes;

a second non-volatile memory array device comprising a plurality of planes; and

a functional device electrically connecting to the first non-volatile memory array device and the second non-volatile memory array device, wherein the functional device comprises:

a z-direction switch configured to select one of the first non-volatile memory array device and the second non-volatile memory array device; and

a plane switch configured to select one of the planes of the selected first non-volatile memory array device or to select one of the planes of the selected second non-volatile memory array device;

a controller disposed on the substrate and electrically connected to the plurality of three dimensional semiconductor device stacks;

a memory device disposed on the substrate and electrically connected to the plurality of three dimensional semiconductor device stacks; and

an I/O interface disposed on the substrate and electrically connected to the plurality of three dimensional semiconductor device stacks.

14 . The system of claim 13 , wherein the controller is configured to operate following steps:

applying a plurality of signals to an input of the z-direction switch of the functional device;

selecting one of the first non-volatile memory array device and the second non-volatile memory array device to send the signals to by the z-direction switch;

applying the signals to the plane switch of the functional device; and

selecting one of the plurality of planes of the selected first non-volatile memory array device or selecting one of the plurality of planes of the selected second non-volatile memory array device by the plane switch.

15 . The system of claim 14 , wherein the controller is configured to send the signals to the selected plane of the selected first non-volatile memory array device or the selected second non-volatile memory array device.

16 . The system of claim 14 , wherein the signals comprise voltage signals, address signals, command signals, state signals, and data signals.

17 . The system of claim 13 , wherein the first non-volatile memory array device, the second non-volatile memory array device, and the functional device are vertically stacked.

18 . A system having three dimensional semiconductor device stacks, the system comprising:

a substrate;

a plurality of three dimensional semiconductor device stacks disposed on the substrate, wherein each of the plurality of three dimensional semiconductor device stacks comprises:

a first non-volatile memory array device comprising a plurality of planes;

a second non-volatile memory array device comprising a plurality of planes; and

a functional device electrically connecting to the first non-volatile memory array device and the second non-volatile memory array device, wherein the functional device comprises:

a z-direction switch configured to select one of the first non-volatile memory array device and the second non-volatile memory array device;

at least one bias voltage generator, at least one register, at least one automaton, and at least one buffer connected to the z-direction switch; and

a plane switch configured to select one of the planes of the selected first non-volatile memory array device or to select one of the planes of the selected second non-volatile memory array device;

a controller disposed on the substrate and electrically connected to the plurality of three dimensional semiconductor device stacks;

a memory device disposed on the substrate and electrically connected to the plurality of three dimensional semiconductor device stacks; and

an I/O interface disposed on the substrate and electrically connected to the plurality of three dimensional semiconductor device stacks.

19 . A system having three dimensional semiconductor device stacks, the system comprising:

a substrate;

a plurality of three dimensional semiconductor device stacks disposed on the substrate, wherein each of the plurality of three dimensional semiconductor device stacks comprises:

a first non-volatile memory array device comprising a plurality of planes;

a second non-volatile memory array device comprising a plurality of planes, wherein each of the first non-volatile memory array device and the second non-volatile memory array device comprises:

a layer stack comprising a plurality of conductive layers and a plurality of insulating layers alternately arranged, wherein lengths of the conductive layers and the underlying insulating layers are sequentially decrease from bottom to top;

a plurality of vertical channel structures disposed in an array region of the layer stack; and

 a plurality of contacts disposed in a stair case region of the layer stack and connected to the conductive layers; and

a functional device electrically connecting to the first non-volatile memory array device and the second non-volatile memory array device and disposed above the first non-volatile memory array device and the second non-volatile memory array device, wherein the functional device comprises:

a z-direction switch configured to select one of the first non-volatile memory array device and the second non-volatile memory array device; and

a plane switch configured to select one of the planes of the selected first non-volatile memory array device or to select one of the planes of the selected second non-volatile memory array device;

a controller disposed on the substrate and electrically connected to the plurality of three dimensional semiconductor device stacks;

a memory device disposed on the substrate and electrically connected to the plurality of three dimensional semiconductor device stacks; and

an I/O interface disposed on the substrate and electrically connected to the plurality of three dimensional semiconductor device stacks.