Vertical transport field-effect transistor with late fin cut
One or more devices and/or methods provided herein relate to a method for fabricating a semiconductor device, and more particularly for fabricating at least a portion of a vertical transport field effect transistor. The semiconductor device comprises a field-effect transmitter comprising a substrate, a fin extending outwardly from the substrate, a source/drain region having a first portion disposed between the substrate and the fin and stacked with the fin and the substrate along a common extension direction of the fin, and an excess section of semiconductor material disposed adjacent the first portion of the source/drain region and positioned other than stacked together with the substrate and the fin, wherein the semiconductor material of the excess section is different from a material of the fin and different from a material of the source/drain region.
1 . A semiconductor device, comprising:
a field-effect transistor comprising:
a substrate;
a fin extending outwardly from the substrate;
a source/drain region having a first portion disposed between the substrate and the fin and stacked with the fin and the substrate along a common extension direction of the fin;
an excess section of semiconductor material, which is different from a material of the fin and different from a material of the source/drain region, wherein the excess section is disposed adjacent the first portion of the source/drain region and positioned other than stacked together with the substrate and the fin; and
a dopant-resistant barrier layer stacked together with and disposed between the fin and the source/drain region along the common extension direction of the fin, wherein the dopant-resistant barrier layer further extends along and covers the excess section.
2 . The semiconductor device of claim 1 , further comprising:
a shallow trench isolation (STI) section, wherein the excess section is disposed between the STI section and the first portion of the source/drain region.
3 . The semiconductor device of claim 1 , where the excess section of semiconductor material comprises silicon-based material.
4 . The semiconductor device of claim 1 , wherein the source/drain region has multiple surface heights facing the fin.
5 . The semiconductor device of claim 1 , further comprising:
a second fin, wherein the fin is a first fin, wherein the source/drain region has a third portion disposed directly between the substrate and the second fin, and wherein the source/drain region extends continuously from the first portion to the third portion along a second portion disposed between the first portion and the third portion.
6 . The semiconductor device of claim 1 , further comprising:
a depression formed adjacent the fin into a surface of the source/drain region facing the fin.
7 . A semiconductor device, comprising:
a field-effect transistor comprising:
a substrate;
a first fin extending outwardly from the substrate;
a source/drain region having a first portion disposed between the substrate and the first fin and stacked with the first fin and the substrate along a common extension direction of the first fin;
an excess section of semiconductor material, which is different from a material of the first fin and different from a material of the source/drain region, wherein the excess section is disposed adjacent the first portion of the source/drain region and positioned other than stacked together with the substrate and the first fin; and
a second fin, wherein the source/drain region has a third portion disposed directly between the substrate and the second fin, and wherein the source/drain region extends continuously from the first portion to the third portion along a second portion disposed between the first portion and the third portion.
8 . The semiconductor device of claim 7 , further comprising:
a shallow trench isolation (STI) section, wherein the excess section is disposed between the STI section and the first portion of the source/drain region.
9 . The semiconductor device of claim 7 , where the excess section of semiconductor material comprises silicon-based material.
10 . The semiconductor device of claim 7 , further comprising a dopant-resistant barrier layer stacked together with and disposed between the first fin and the source/drain region along the common extension direction of the first fin.
11 . The semiconductor device of claim 10 , wherein the dopant-resistant barrier layer further extends along and covers the excess section.
12 . The semiconductor device of claim 7 , wherein the source/drain region has multiple surface heights facing the first fin.
13 . The semiconductor device of claim 7 , further comprising:
a depression formed adjacent the first fin into a surface of the source/drain region facing the first fin.