Nanosheet structures with corner spacer
The present disclosure relates to semiconductor structures and, more particularly, to nanosheet transistor structures and methods of manufacture. The structure includes: a plurality of stacked semiconductor nanosheets over a semiconductor substrate; a plurality of gate structures surrounding individual nanosheets of the plurality of semiconductor nanosheets; an inner sidewall spacer adjacent each of the plurality of gate structures; and corner spacers under the plurality of stacked semiconductor nanosheets.
1 . A structure comprising:
a plurality of stacked semiconductor nanosheets over a semiconductor substrate;
a plurality of gate structures surrounding individual nanosheets of the plurality of semiconductor nanosheets;
an inner sidewall spacer adjacent each of the plurality of gate structures; and
corner spacers under the plurality of stacked semiconductor nanosheets,
wherein the corner spacers have an outer vertical sidewall which is entirely aligned with an outside vertical sidewall of the inner sidewall spacer and an inner vertical sidewall which is non-aligned in a vertical direction with an inner vertical sidewall of the inner sidewall spacer.
2 . The structure of claim 1 , wherein the corner spacers comprise insulator material.
3 . The structure of claim 1 , wherein the corner spacers extend partially underneath a bottommost inner sidewall spacer.
4 . The structure of claim 1 , wherein the corner spacers extend underneath the bottommost inner sidewall spacer.
5 . The structure of claim 1 , wherein the corner spacers extend to underneath the plurality of gate structures.
6 . The structure of claim 1 , further comprising source/drain regions on opposing sides of the plurality of gate structures, wherein the corner spacers are between the source/drain regions.
7 . The structure of claim 6 , wherein the corner spacers are within the semiconductor substrate.
8 . The structure of claim 7 , wherein the corner spacers are below the source/drain regions.
9 . The structure of claim 6 , further comprising a counter doped region under the source/drain regions, and the counter doped region has a conductivity type which is opposite to the source/drain regions.
10 . The structure of claim 9 , wherein the counter doped region is below the corner spacers.
11 . The structure of claim 1 , wherein the corner spacers extend below a bottommost channel region comprising a bottommost semiconductor nanosheet of the plurality of stacked semiconductor nanosheets.
12 . The structure of claim 1 , further comprising a counter doped region which partially overlaps with the corner spacers.
13 . A structure comprising:
a fin structure comprising at least one gate structure;
a source region on a first side of the at least one gate structure;
a drain region on a second side of the at least one gate structure; and
corner spacers below the fin structure, the source region and the drain region,
wherein the corner spacers have an outer vertical sidewall which is entirely vertically aligned with an outside vertical sidewall of the inner sidewall spacer and have an inner vertical sidewall which is non-aligned in a vertical direction with an inner vertical sidewall of the inner sidewall spacer.
14 . The structure of claim 13 , wherein the fin structure is above semiconductor material, and the corner spacers comprise insulator material within the semiconductor material.
15 . The structure of claim 13 , wherein the fin structure comprises a plurality of stacked semiconductor nanosheets, the at least one gate structure comprises a plurality of gate structures wrapping around individual semiconductor nanosheets of the stacked semiconductor nanosheets, and the source region and the drain region are raised regions adjacent to the plurality of gate structures.
16 . The structure of claim 15 , further comprising inner spacers adjacent to each of the plurality of gate structures and between the semiconductor nanosheets, the inner spacers separating each of the plurality of gate structures from the source region and from the drain region, and the corner spacers extend at least partially underneath a bottommost inner spacer of the inner spacers.
17 . The structure of claim 16 , wherein the corner spacers extend to underneath the plurality of gate structures.
18 . The structure of claim 16 , further comprising a counter doped region under the source region and the drain region, and the counter doped region has a conductivity type which is opposite to the source region and the drain region.
19 . The structure of claim 18 , wherein the counter doped region partially overlaps with the corner spacers, and the counter doped region is below the corner spacers.
20 . A method comprising:
forming a plurality of stacked semiconductor nanosheets over a semiconductor substrate;
forming a plurality of gate structures surrounding individual nanosheets of the plurality of semiconductor nanosheets;
forming an inner sidewall spacer adjacent each of the plurality of gate structures; and
forming corner spacers under the plurality of stacked semiconductor nanosheets,
wherein the corner spacers have an outer vertical sidewall which is entirely aligned with an outside vertical sidewall of the inner sidewall spacer and an inner vertical sidewall which is non-aligned in a vertical direction with an inner vertical sidewall of the inner sidewall spacer.