Barrier structure for dispersion reduction in transistor devices
Transistor devices are provided. In one example, the transistor device includes a channel layer. The transistor device includes a multilayer barrier structure on the channel layer. The multilayer barrier structure includes a first Group III-nitride layer and a second Group III-nitride layer on the first Group III-nitride layer and opposite to the channel layer. The first Group III-nitride layer has a thickness greater than a thickness of the second Group III-nitride layer. An aluminum concentration of the first Group III-nitride layer is at least two times greater than an aluminum concentration of the second Group III-nitride layer.
1 . A transistor device, comprising:
a channel layer; and
a multilayer barrier structure on the channel layer, the multilayer barrier structure comprising a first Group III-nitride layer and a second Group III-nitride layer on the first Group III-nitride layer and opposite to the channel layer, the first Group III-nitride layer having a thickness greater than a thickness of the second Group III-nitride layer, wherein an aluminum concentration of the first Group III-nitride layer is at least two times greater than an aluminum concentration of the second Group III-nitride layer;
wherein the thickness of the second Group III-nitride layer is about 50 Angstroms or less and a ratio of the thickness of the first Group III-nitride layer to the thickness of the second Group III-nitride layer is greater than 4:1.
2 . The transistor device of claim 1 , wherein the thickness of the second Group III-nitride layer is about 50 Angstroms or less, and the aluminum concentration of the second Group III-nitride layer is about 1% to about 10%, such that a current collapse of the transistor device after a stress condition is about 30% or less at a 0V gate voltage relative to operation of the transistor device prior to the stress condition, wherein the stress condition comprises a 10-millisecond pulse of a 100V drain voltage and a −8V gate voltage.
3 . The transistor device of claim 1 , wherein the aluminum concentration of the first Group III-nitride layer is at least five times greater than the aluminum concentration of the second Group III-nitride layer.
4 . The transistor device of claim 1 , wherein an aluminum mole fraction of the first Group III-nitride layer is in a range of about 20% to about 100%.
5 . The transistor device of claim 4 , wherein an aluminum mole fraction of the second Group III-nitride layer is in a range of about 1% to about 10%.
6 . The transistor device of claim 1 , wherein the thickness of the first Group III-nitride layer is over 200 Angstroms to about 250 Angstroms.
7 . The transistor device of claim 1 , wherein the multilayer barrier structure comprises an interface layer, the first Group III-nitride layer being disposed on the interface layer and opposite the channel layer, wherein an aluminum concentration of the interface layer is greater than the aluminum concentration of the first Group III-nitride layer and the aluminum concentration of the second Group III-nitride layer.
8 . The transistor device of claim 7 , wherein a thickness of the interface layer is in a range of about 50 Angstroms or less.
9 . The transistor device of claim 1 , further comprising a source contact and a drain contact on the multilayer barrier structure.
10 . The transistor device of claim 1 , wherein the second Group III-nitride layer has a graded concentration of aluminum that increases such that the second Group III-nitride layer has a higher aluminum concentration at an interface between the first Group III-nitride layer and the second Group III-nitride layer relative to a surface of the second Group III-nitride layer opposite the first Group III-nitride layer.
11 . The transistor device of claim 1 , further comprising a cap layer on the multilayer barrier structure.
12 . The transistor device of claim 1 , wherein the transistor device is a high electron mobility transistor.
13 . The transistor device of claim 1 , wherein the channel layer is disposed on a silicon carbide substrate.
14 . A transistor device, comprising:
a channel layer; and
a multilayer barrier structure on the channel layer, the multilayer barrier structure comprising a first Group III-nitride layer and a second Group III-nitride layer on the first Group III-nitride layer and opposite to the channel layer, the first Group III-nitride layer having a thickness at least four times greater than a thickness of the second Group III-nitride layer, wherein an aluminum concentration of the first Group III-nitride layer is greater than an aluminum concentration of the second Group III-nitride layer;
wherein the thickness of the second Group III-nitride layer is about 50 Angstroms or less and a ratio of the thickness of the first Group III-nitride layer to the thickness of the second Group III-nitride layer is greater than 4:1.
15 . The transistor device of claim 14 , wherein the thickness of the second Group III-nitride layer is about 50 Angstroms or less, and the aluminum concentration of the second Group III-nitride layer is about 1% to about 10%, such that a pinch-off voltage shift of the transistor device after a stress condition is about 0.4V or less at a 50V drain voltage relative to operation of the transistor device prior to the stress condition, wherein the stress condition comprises a 10-millisecond pulse of a 100V drain voltage and a −8V gate voltage.
16 . The transistor device of claim 14 , wherein the multilayer barrier structure comprises an interface layer, the first Group III-nitride layer being disposed on the interface layer and opposite the channel layer, wherein an aluminum concentration of the interface layer is greater than the aluminum concentration of the first Group III-nitride layer and the aluminum concentration of the second Group III-nitride layer.
17 . The transistor device of claim 16 , wherein a thickness of the interface layer is in a range of about 50 Angstroms or less.
18 . The transistor device of claim 14 , wherein the aluminum concentration of the first Group III-nitride layer is at least two times greater than the aluminum concentration of the second Group III-nitride layer.
19 . A transistor device, comprising:
a channel layer; and
a multilayer barrier structure on the channel layer, the multilayer barrier structure comprising a first layer on the channel layer, a second layer on the first layer, and a third layer on the second layer;
wherein the first layer is an Al x Ga 1-x N layer where x≥0.5;
wherein the second layer is Al y Ga 1-y N layer where 0.2≤y<1;
wherein the third layer is an Al z Ga 1-z N layer where 0<z≤0.1;
wherein a ratio of a thickness of the second layer to a thickness of the third layer is 4:1 or greater.
20 . The transistor device of claim 19 , further comprising a silicon carbide substrate.
21 . A transistor device, comprising:
a channel layer; and
a multilayer Group III-nitride based barrier structure on the channel layer, the multilayer Group III-nitride based barrier structure comprising a first layer and a second layer on the first layer, wherein a thickness of the second layer or an aluminum concentration of the second layer is such that a current collapse of the transistor device after a stress condition is about 30% or less at a 0V gate voltage relative to operation of the transistor device prior to the stress condition, wherein the stress condition comprises a 10-millisecond pulse of a 100V drain voltage and a −8V gate voltage;
wherein the thickness of the second layer is about 50 Angstroms or less and a ratio of the thickness of the first Group III-nitride layer to the thickness of the second Group III-nitride layer is greater than 4:1.
22 . The transistor device of claim 21 , wherein an aluminum concentration of the first layer is at least two times greater than the aluminum concentration of the second layer at an interface between the first layer and the second layer.
23 . A transistor device, comprising:
a channel layer; and
a multilayer Group III-nitride based barrier structure on the channel layer, the multilayer Group III-nitride based barrier structure comprising a first layer and a second layer on the first layer, wherein a thickness of the second layer or an aluminum concentration of the second layer is such that a pinch-off voltage shift of the transistor device after a stress condition is about 0.4V or less at a 50V drain voltage relative to operation of the transistor device prior to the stress condition, wherein the stress condition comprises a 10-millisecond pulse of a 100V drain voltage and a −8V gate voltage;
wherein the thickness of the second layer is about 50 Angstroms or less and a ratio of the thickness of the first Group III-nitride layer to the thickness of the second Group III-nitride layer is greater than 4:1.
24 . The transistor device of claim 23 , wherein an aluminum concentration of the first layer is at least two times greater than the aluminum concentration of the second layer at an interface between the first layer and the second layer.