Semiconductor device and method of forming the same
A method of forming a semiconductor device includes forming a dummy gate structure across a fin protruding from a substrate, forming gate spacers on opposite sidewalls of the dummy gate structure, forming source/drain epitaxial structures on opposite sides of the dummy gate structure, forming a first interlayer dielectric (ILD) layer on the source/drain epitaxial structures and outer sidewalls of the gate spacers, replacing the dummy gate structure with a replacement gate structure, etching back the replacement gate structure to form a first recess between the gate spacers, forming a source/drain contact in the first ILD layer, and forming a second interlayer dielectric (ILD) layer to fill in the first recess between the gate spacers and over the source/drain contact.
1 . A method of forming a semiconductor device, comprising:
forming a dummy gate structure across a fin protruding from a substrate;
forming gate spacers on opposite sidewalls of the dummy gate structure;
forming source/drain epitaxial structures on opposite sides of the dummy gate structure;
forming a first interlayer dielectric (ILD) layer on the source/drain epitaxial structures and outer sidewalls of the gate spacers;
replacing the dummy gate structure with a replacement gate structure;
etching back the replacement gate structure to form a first recess between the gate spacers;
forming a source/drain contact in the first ILD layer; and
forming a second interlayer dielectric (ILD) layer to fill in the first recess between the gate spacers and over the source/drain contact, wherein the source/drain contact has a top surface higher than a bottommost surface of the second ILD layer.
2 . The method of claim 1 , wherein forming the source/drain contact in the first ILD layer comprises:
forming a patterned photoresist on the first ILD layer having an opening exposing a part of the first ILD layer on the source/drain epitaxial structures;
removing the part of the first ILD layer to form a space; and
filling the space with a conductive material.
3 . The method of claim 1 , further comprising:
forming a hard mask layer on the replacement gate structure to fill the first recess before forming the source/drain contact in the first ILD layer.
4 . The method of claim 3 , further comprising:
removing the hard mask layer after forming the source/drain contact in the first ILD layer to expose the replacement gate structure.
5 . The method of claim 1 , further comprising:
forming an etch stop layer lining the first recess between the gate spacers.
6 . The method of claim 1 , further comprising:
after etching back the replacement gate structure, forming a hard mask layer in the first recess; and
removing the hard mask layer to expose the replacement gate structure.
7 . The method of claim 1 , wherein the source/drain contact has a bottom surface level with a bottom surface of the replacement gate structure.
8 . The method of claim 1 , further comprising:
forming a first via plug over the source/drain contact, wherein the first via plug has a bottom surface higher than the bottommost surface of the second ILD layer.
9 . The method of claim 8 , further comprising:
forming a second via plug over the replacement gate structure, wherein the first via plug and the second via plug have different heights along a vertical direction.
10 . A method of forming a semiconductor device, comprising:
forming a fin extending in a first direction above a substrate;
forming a gate structure across the fin and extending in a second direction substantially perpendicular to the first direction;
forming gate spacers on opposite sides of the gate structure, respectively, wherein the gate spacers and the gate structure have a recess between the gate spacers;
forming source/drain regions adjacent the gate spacers, respectively;
forming source/drain contacts on the source/drain regions, respectively, wherein the source/drain contacts have a top surface level with a top surface of the gate spacers;
forming a first interlayer dielectric (ILD) layer over the gate structure and the source/drain contacts, the first ILD layer having a portion extending between the gate spacers; and
forming a second interlayer dielectric (ILD) layer to fill in the recess between the gate spacers and over the source/drain contacts, wherein the source/drain contacts have the top surface higher than a bottommost surface of the second ILD layer.
11 . The method of claim 10 , further comprising:
forming an etch stop layer extending across the gate structure and the gate spacers, wherein the etch stop layer has a bottom surface higher over the gate spacers than over the gate structure.
12 . The method of claim 11 , wherein each of the gate spacers has an inner sidewall having a lower region interfacing the gate structure and an upper region interfacing the etch stop layer.
13 . The method of claim 10 , wherein a bottom surface of the first ILD layer is lower on the gate structure than on the source/drain contacts.
14 . The method of claim 10 , further comprising:
forming a silicide region over one of the source/drain regions, the silicide region has a bottom surface lower than a bottom surface of the gate structure.
15 . A method of forming a semiconductor device, comprising:
forming source/drain epitaxial structures over a substrate;
forming a first interlayer dielectric (ILD) layer over the source/drain epitaxial structures;
forming a gate structure over the substrate, wherein the source/drain epitaxial structures are on opposites sides of the gate structure;
forming gate spacers on opposite sides of the gate structure, respectively, wherein the gate spacers and the gate structure have a recess between the gate spacers;
forming source/drain contacts over the source/drain epitaxial structures; and
after forming the source/drain contacts over the source/drain epitaxial structures, forming a second interlayer dielectric (ILD) layer over the first ILD layer, wherein the second ILD layer has a bottom surface lower than a top surface of the first ILD layer, and wherein forming the second ILD layer comprises:
forming the second ILD layer to fill in the recess between the gate spacers and over the source/drain contacts, wherein the source/drain contacts have a top surface higher than a bottommost surface of the second ILD layer.
16 . The method of claim 15 , further comprising:
an etch stop layer over the first ILD layer, wherein the etch stop layer has a bottom surface lower than the top surface of the first ILD layer.
17 . The method of claim 16 ,
wherein the etch stop layer and the second ILD layer have a first interface lower than the top surface of one of the source/drain contacts.
18 . The method of claim 17 , wherein the etch stop layer and the second ILD layer have a second interface higher than the top surface of the source/drain contact.
19 . The method of claim 17 , wherein the gate structure has a vertical thickness smaller than a vertical thickness of the source/drain contact.
20 . The method of claim 15 , further comprising:
forming an etch stop layer over the source/drain contacts, wherein one of the source/drain contacts is in contact with the etch stop layer.