IP Library › Granted Patent US 12672308
Granted Patent B2
US 12672308 · App. 19/274,412 · Granted Jun 30, 2026

Thin-film transistors with gate-source capacitance tuning

Inventors: Douglas W. Barlage (Edmonton, CA); Viraj Bhingardive (Edmonton, CA); Korel Dawkins (Edmonton, CA); Alex Ma (Edmonton, CA); Eric Wilson Milburn (Edmonton, CA); Lhing Gem Shoute (Edmonton, CA)
Assignee: ZINITE CORPORATION
H10D30/6706H10D30/0314H10D30/6731H10D30/6736H10D30/6757
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Quick Facts
Patent No.
US 12672308
App. No.
19/274,412
Granted
Jun 30, 2026
Kind
B2
Abstract

An example thin-film transistor includes a source and a gate. The source includes a body of source metal and a body of capacitance-tuning material disposed on the body of source metal. The body of capacitance-tuning material is configured to control a capacitance between the source and the gate. A drain of the thin-film transistor may also include a body of capacitance-tuning material. Capacitance-tuning material may be provided outside the source/drain, for example, adjacent a gate dielectric material. The thin-film transistor may further include a body of reducing material to draw oxygen out of other materials of the thin-film transistor. The thin-film transistor may further include a body of hardmask material used during the making of the thin-film transistor.

Claims (44)

1 . A thin-film transistor comprising a stack of layers formed of:

a layer of source material;

a layer of capacitance-tuning material formed over and in contact with the layer of source material;

a layer of semiconductor channel material formed over at least the layer of capacitance-tuning material, the layer of semiconductor channel material in contact with the layer of source material;

a layer of gate dielectric material formed over and in contact with the layer of semiconductor channel material;

a layer of encapsulation material formed over and in contact with the layer of gate dielectric material; and

a layer of conductive gate material formed over and in contact with the layer of encapsulation material;

wherein a capacitance between the layer of source material and the layer of gate material is dependent on properties of at least the layer of gate dielectric material, the layer of capacitance-tuning material, and the layer of encapsulation material; and

wherein at least one property of the layer of capacitance-tuning material is selected to control the capacitance between the layer of source material and the layer of gate material.

2 . The thin-film transistor of claim 1 , wherein the at least one property of the layer of capacitance-tuning material is selected to reduce the capacitance between the layer of source material and the layer of gate material.

3 . The thin-film transistor of claim 1 , wherein the layer of capacitance-tuning material comprises silicon dioxide.

4 . The thin-film transistor of claim 1 , further comprising a layer of reducing material formed over and in contact with the layer of capacitance-tuning material, wherein the layer of reducing material is configured to draw oxygen out of another material of the thin-film transistor.

5 . The thin-film transistor of claim 4 , wherein the layer of reducing material is in contact with the layer of semiconductor channel material.

6 . The thin-film transistor of claim 1 , further comprising:

a layer of drain material;

another layer of capacitance-tuning material formed over and in contact with the layer of drain material;

another layer of encapsulation material formed over and in contact with the layer of gate dielectric material; and

wherein a capacitance between the layer of drain material and the layer of gate material is dependent on properties of at least the layer of gate dielectric material, the other layer of capacitance-tuning material, and the other layer of encapsulation material; and

wherein at least one property of the other layer of capacitance-tuning material is selected to control the capacitance between the layer of drain material and the layer of gate material.

7 . A method of making a thin-film transistor, the method comprising forming a stack of layers by:

forming a layer of source material;

forming a layer of capacitance-tuning material in contact with the layer of source material;

forming a layer of semiconductor channel material over at least the layer of capacitance-tuning material, the layer of semiconductor channel material in contact with the layer of source material;

forming a layer of gate dielectric material over and in contact with the layer of semiconductor channel material;

forming a layer of encapsulation material over and in contact with the layer of gate dielectric material; and

forming a layer of conductive gate material over and in contact with the layer of encapsulation material;

wherein a capacitance between the layer of source material and the layer of gate material is dependent on properties of at least the layer of gate dielectric material, the layer of capacitance-tuning material, and the layer of encapsulation material; and

wherein at least one property of the layer of capacitance-tuning material is selected to control the capacitance between the layer of source material and the layer of gate material.

8 . The method of claim 7 , wherein the at least one property of the layer of capacitance-tuning material is selected to reduce the capacitance between the layer of source material and the layer of gate material.

9 . The method of claim 7 , wherein forming the layer of capacitance-tuning material comprises forming a layer of silicon dioxide using atomic layer deposition.

10 . The method of claim 7 , further comprising forming a layer of reducing material over and in contact with the layer of capacitance-tuning material, wherein the layer of reducing material is configured to draw oxygen out of another material of the thin-film transistor.

11 . The method of claim 7 , further comprising forming a layer of mask material on the layer of capacitance-tuning material, wherein the layer of mask material is used to etch the capacitance-tuning material to form the layer of capacitance-tuning material and/or to etch the source material to form the layer of source material.

12 . The method of claim 11 , wherein the layer of mask material remains in the thin-film transistor after the making of the thin-film transistor.

13 . The method of claim 11 , wherein the layer of mask material is formed between the layer of capacitance-tuning material and the layer of semiconductor channel material.

14 . The method of claim 7 , further comprising:

forming a layer of drain material;

forming another layer of capacitance-tuning material over and in contact with the layer of drain material;

forming another layer of encapsulation material over and in contact with the layer of gate dielectric material; and

wherein a capacitance between the layer of drain material and the layer of gate material is dependent on properties of at least the layer of gate dielectric material, the other layer of capacitance-tuning material, and the other layer of encapsulation material; and

wherein at least one property of the other layer of capacitance-tuning material is selected to control the capacitance between the layer of drain material and the layer of gate material.

15 . The thin-film transistor of claim 1 , wherein at least one property of the layer of encapsulation material is selected to further control the capacitance between the layer of source material and the layer of gate material.

16 . The thin-film transistor of claim 15 , wherein at least one property of the layer of encapsulation material is selected to reduce the capacitance between the layer of source material and the layer of gate material.

17 . The method of claim 7 , wherein at least one property of the layer of encapsulation material is selected to further control the capacitance between the layer of source material and the layer of gate material.

18 . The method of claim 17 , wherein at least one property of the layer of encapsulation material is selected to reduce the capacitance between the layer of source material and the layer of gate material.