Semiconductor structures with wrap-around contact structure

1 . A semiconductor structure, comprising:

a source/drain region having a top surface and a bottom surface, the top surface of the source/drain region comprising a recessed portion within the source/drain region and the bottom surface being disposed on a bottom dielectric isolation layer;

a metal contact having a first portion and a second portion, wherein the first portion of the metal contact has a first width and the second portion of the metal contact has a second width greater than the first width, wherein at least a portion of the second portion of the metal contact is disposed in the recessed portion within the source/drain region; and

a sidewall spacer disposed on sidewalls of the bottom dielectric isolation layer and the source/drain region;

wherein the bottom surface of the source/drain region and the bottom dielectric isolation layer are continuous between the sidewall spacer disposed on the sidewalls of the bottom dielectric isolation layer and the source/drain region.

2 . The semiconductor structure according to claim 1 , wherein a top surface of the second portion of the metal contact extends above the top surface of the source/drain region.

3 . The semiconductor structure according to claim 2 , wherein the sidewall spacer is further disposed on sidewalls of the second portion of the metal contact.

4 . The semiconductor structure according to claim 1 , wherein a top surface of the second portion of the metal contact is coplanar with the top surface of the source/drain region.

5 . The semiconductor structure according to claim 1 , wherein the recessed portion of the source/drain region is one of a u-shaped surface or a v-shaped surface.

6 . The semiconductor structure according to claim 1 , further comprising the source/drain region disposed between a first channel region and a second channel region.

7 . An integrated circuit, comprising:

a plurality of semiconductor structures, wherein at least one of the plurality of semiconductor structures comprises:

a source/drain region having a top surface and a bottom surface, the top surface of the source/drain region comprising a recessed portion within the source/drain region and the bottom surface being disposed on a bottom dielectric isolation layer;

a metal contact having a first portion and a second portion, wherein the first portion of the metal contact has a first width and the second portion of the metal contact has a second width greater than the first width, wherein at least a portion of the second portion of the metal contact is disposed in the recessed portion within the source/drain region; and

a sidewall spacer disposed on sidewalls of the bottom dielectric isolation layer and the source/drain region;

wherein the bottom surface of the source/drain region and the bottom dielectric isolation layer are continuous between the sidewall spacer disposed on the sidewalls of the bottom dielectric isolation layer and the source/drain region.

8 . The integrated circuit according to claim 7 , wherein a top surface of the second portion of the metal contact extends above the top surface of the source/drain region.

9 . The integrated circuit according to claim 8 , wherein the sidewall spacer is further disposed on sidewalls of the second portion of the metal contact.

10 . The integrated circuit according to claim 7 , wherein a top surface of the second portion of the metal contact is coplanar with the top surface of the source/drain region.

11 . The integrated circuit according to claim 7 , wherein the recessed portion of the source/drain region is one of a u-shaped surface or a v-shaped surface.

12 . The integrated circuit according to claim 7 , wherein the at least one of the plurality of semiconductor structures further comprises the source/drain region disposed between a first channel region and a second channel region.

13 . A method, comprising:

forming a source/drain region having a top surface and a bottom surface, the top surface of the source/drain region comprising a recessed portion within the source/drain region and the bottom surface being disposed on a bottom dielectric isolation layer;

forming a metal contact in the source/drain region, the metal contact having a first portion and a second portion, wherein the first portion of the metal contact has a first width and the second portion of the metal contact has a second width greater than the first width, wherein at least a portion of the second portion of the metal contact is formed in the recessed portion within the source/drain region; and

forming a sidewall spacer on sidewalls of the bottom dielectric isolation layer and the source/drain region;

wherein the bottom surface of the source/drain region and the bottom dielectric isolation layer are continuous between the sidewall spacer disposed on the sidewalls of the bottom dielectric isolation layer and the source/drain region.

14 . The method according to claim 13 , wherein a top surface of the second portion of the metal contact extends above the top surface of the source/drain region.

15 . The method according to claim 14 , further comprising forming the sidewall spacer on sidewalls of the second portion of the metal contact.

16 . The method according to claim 13 , wherein a top surface of the second portion of the metal contact is coplanar with the top surface of the source/drain region.

17 . The semiconductor structure according to claim 1 , further comprising a metal-containing liner disposed on the metal contact.

18 . The integrated circuit according to claim 7 , wherein the at least one of the plurality of semiconductor structures further comprises a metal-containing liner disposed on the metal contact.

19 . The method according to claim 13 , wherein the recessed portion of the source/drain region is one of a u-shaped surface or a v-shaped surface.

20 . The method according to claim 13 , further comprising forming the source/drain region between a first channel region and a second channel region.