IP Library Granted Patent US 12672310
Granted Patent B2
US 12672310 · App. 18/138,122 · Granted Jun 30, 2026

Transistor

Inventors: Seungjun Lee (Suwon-si, KR); Sang Sig Kim (Seoul, KR); Jun Hyung Lim (Seoul, KR); Kyoung Ah Cho (Seoul, KR); Hee Sung Kong (Seoul, KR)
Assignees: Samsung Display Co., Ltd.; Korea University Research and Business Foundation
H10D30/6734H10D30/6755
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Quick Facts
Patent No.
US 12672310
App. No.
18/138,122
Granted
Jun 30, 2026
Kind
B2
Abstract

A transistor is disclosed that includes an active layer and a gate electrode. The active layer includes a first conductor layer including metal atoms, a layer of semiconductor material disposed above the first conductor layer, and a second conductor layer disposed above the semiconductor material layer and including the metal atoms. The gate electrode overlaps a part of the active layer and is electrically insulated from the active layer.

Claims (38)

1 . A transistor comprising:

an active layer including a first conductor layer including metal atoms, a semiconductor material layer disposed above the first conductor layer, and a second conductor layer disposed above the semiconductor material layer and including the metal atoms;

a gate electrode overlapping a part of the active layer and electrically insulated from the active layer; and

a source-drain electrode overlapping an other part of the active layer different from the part of the active layer and electrically contacting the active layer,

wherein the gate electrode overlaps the first conductive layer, the semiconductor material layer, and the second conductive layer and does not overlap the source-drain electrode, and

wherein the first conductor layer induces the formation of a channel in a lower part of the semiconductor material layer adjacent to the first conductor layer, and the second conductor layer induces the formation of the channel in an upper part of the semiconductor material layer adjacent to the second conductor layer.

2 . The transistor of claim 1 , wherein the semiconductor material layer includes an oxide semiconductor material.

3 . The transistor of claim 1 , wherein the semiconductor material layer is a single layer.

4 . The transistor of claim 1 , wherein each of the first conductor layer and the second conductor layer further includes oxygen atoms.

5 . The transistor of claim 4 , wherein each of the first conductor layer and the second conductor layer includes at least one of indium tin oxide (ITO) and indium zinc oxide (IZO).

6 . The transistor of claim 1 , wherein the semiconductor material layer has a thickness greater than a sum of a thickness of the first conductor layer and a thickness of the second conductor layer.

7 . The transistor of claim 1 , wherein the first conductor layer has a thickness of 0.1 nm or more and 5 nm or less, and the second conductor layer has a thickness of 0.1 nm or more and 5 nm or less.

8 . The transistor of claim 1 , wherein the gate electrode includes:

a first gate electrode disposed below the active layer and overlapping with the part of the active layer; and

a second gate electrode disposed above the active layer and overlapping with the part of the active layer.

9 . The transistor of claim 8 , further comprising:

a first gate insulating layer disposed between the first gate electrode and the active layer, and electrically insulating the first gate electrode from the active layer; and

a second gate insulating layer disposed between the second gate electrode and the active layer, and electrically insulating the second gate electrode from the active layer.

10 . A transistor comprising:

a plurality of active layers each including a first conductor layer including metal atoms, a semiconductor material layer disposed above the first conductor layer, and a second conductor layer disposed above the semiconductor material layer and including the metal atoms, and arranged in a direction while being spaced apart from each other in the direction;

a gate electrode overlapping with a part of each of the active layers and electrically insulated from the active layers,

a first source-drain electrode overlapping an other part of each of the active layers different from the part of each of the active layers and electrically contacting the active layers; and

a second source-drain electrode spaced apart from the first source-drain electrode and electrically contacting the active layers,

wherein the active layers are disposed between the same first source-drain electrode and the same second source-drain electrode.

11 . The transistor of claim 10 , wherein the semiconductor material layer includes an oxide semiconductor material.

12 . The transistor of claim 10 , wherein the semiconductor material layer is a single layer.

13 . The transistor of claim 10 , wherein each of the first conductor layer and the second conductor layer further includes oxygen atoms.

14 . The transistor of claim 13 , wherein each of the first conductor layer and the second conductor layer includes at least one of indium tin oxide (ITO) and indium zinc oxide (IZO).

15 . The transistor of claim 10 , wherein the semiconductor material layer has a thickness greater than a sum of a thickness of the first conductor layer and a thickness of the second conductor layer.

16 . The transistor of claim 10 , wherein the first conductor layer has a thickness of 0.1 nm or more and 5 nm or less, and the second conductor layer has a thickness of 0.1 nm or more and 5 nm or less.

17 . The transistor of claim 10 , wherein the gate electrode covers at least side surfaces of each of the active layers spaced apart from each other.

18 . The transistor of claim 10 , wherein the gate electrode includes:

a first gate electrode disposed below the active layers and overlapping with the part of each of the active layers; and

a second gate electrode disposed above the active layers and overlapping with the part of each of the active layers.

19 . The transistor of claim 18 , wherein the second gate electrode covers at least side surfaces of each of the active layers spaced apart from each other.

20 . The transistor of claim 18 , further comprising:

a first gate insulating layer disposed between the first gate electrode and the active layers and electrically insulating the first gate electrode from the active layer; and

a second gate insulating layer disposed between the second gate electrode and the active layer and electrically insulating the second gate electrode from the active layer.