Integrated circuit device and manufacturing method thereof
A method for fabricating an integrated circuit device includes forming first epitaxial stack comprising a first sacrificial layer and a first channel layer over a substrate; forming a second epitaxial stack comprising a second sacrificial layer and a second channel layer over the first epitaxial stack; etching a recess in the first and second epitaxial stacks, wherein the recess exposes end surfaces of the first and second channel layers; performing a first ion implantation process to form a first lightly doped region; performing a second ion implantation process to form a second lightly doped region, wherein a tilt angle of the second ion implantation process is greater than a tilt angle of the first ion implantation process; forming first and second source/drain epitaxial features in the recess; and replacing the first and the second sacrificial layers with a high-k/metal gate structure.
1 . A method for fabricating an integrated circuit device, comprising:
forming a first epitaxial stack over a substrate, the first epitaxial stack comprising a first sacrificial layer and a first channel layer over the first sacrificial layer;
forming a second epitaxial stack over the first epitaxial stack, the second epitaxial stack comprising a second sacrificial layer and a second channel layer over the second sacrificial layer;
etching a recess in the second epitaxial stack and the first epitaxial stack, wherein the recess exposes end surfaces of the second channel layer and the first channel layer;
performing a first ion implantation process to form a first lightly doped region adjoining the first channel layer;
after performing the first ion implantation process, performing a second ion implantation process to form a second lightly doped region adjoining the second channel layer, wherein a tilt angle of the second ion implantation process is greater than a tilt angle of the first ion implantation process;
forming a first source/drain epitaxial feature in the recess and adjoining the first lightly doped region;
forming a second source/drain epitaxial feature in the recess and adjoining the second lightly doped region; and
replacing the first sacrificial layer and the second sacrificial layer with a high-k/metal gate structure.
2 . The method of claim 1 , wherein the first lightly doped region has a first conductive type different from a second conductive type of the second lightly doped region.
3 . The method of claim 1 , wherein the tilt angle of the first ion implantation process is in a range from 0 degree to 5 degrees.
4 . The method of claim 1 , wherein the tilt angle of the second ion implantation process is in a range from 40 degree to 80 degrees.
5 . The method of claim 1 , further comprising:
depositing a semiconductor layer into the recess prior to the first ion implantation process, wherein the semiconductor layer has a tapered sidewall facing away from the first channel layer.
6 . The method of claim 5 , wherein an angle between the tapered sidewall of the semiconductor layer and a top surface of the substrate is in a range from 5 degrees to 60 degrees.
7 . The method of claim 1 , further comprising:
forming a channel isolation dielectric between the first and second epitaxial stack.
8 . The method of claim 1 , further comprising:
forming a blocking feature over the first source/drain epitaxial feature, wherein forming the second source/drain epitaxial feature is performed such that the second source/drain epitaxial feature is over the blocking feature.
9 . A method for fabricating an integrated circuit device, comprising:
forming a first epitaxial stack over a substrate, the first epitaxial stack comprising a first sacrificial layer and a first channel layer over the first sacrificial layer;
forming a second epitaxial stack over the first epitaxial stack, the second epitaxial stack comprising a second sacrificial layer and a second channel layer over the second sacrificial layer;
forming a recess in the second epitaxial stack and the first epitaxial stack, wherein the recess has an upper sidewall adjacent the second epitaxial stack and a lower sidewall adjacent the first epitaxial stack, and an angle between the upper sidewall and a top surface of the substrate is greater than an angle between the lower sidewall and the top surface of the substrate;
performing a first ion implantation process to form a first lightly doped region adjoining the first channel layer;
after performing the first ion implantation process, performing a second ion implantation process to form a second lightly doped region adjoining the second channel layer;
forming a first source/drain epitaxial feature in the recess and adjoining the first lightly doped region;
forming a second source/drain epitaxial feature in the recess and adjoining the second lightly doped region; and
replacing the first sacrificial layer and the second sacrificial layer with a gate structure.
10 . The method of claim 9 , wherein the angle between the upper sidewall and the top surface of the substrate is in a range from 80 degrees to 90 degrees.
11 . The method of claim 9 , wherein the angle between the lower sidewall and the top surface of the substrate is in a range from 5 degrees to 60 degrees.
12 . The method of claim 9 , wherein forming the recess in the second epitaxial stack and the first epitaxial stack comprises:
etching a recess in the second epitaxial stack and the first epitaxial stack; and
depositing a semiconductor layer into the recess, wherein the semiconductor layer is in contact with the first channel layer but not with the second channel layer.
13 . The method of claim 12 , wherein the semiconductor layer has a sidewall thickness decreasing as a distance from the substrate increases.
14 . The method of claim 9 , wherein a tilt angle of the second ion implantation process is greater than a tilt angle of the first ion implantation process.
15 . The method of claim 9 , wherein the first lightly doped region has a first conductive type different from a second conductive type of the second lightly doped region.
16 . A method comprising:
forming a first epitaxial stack over a substrate, the first epitaxial stack comprising a first sacrificial layer and a first channel layer over the first sacrificial layer;
forming a middle semiconductor layer over the first epitaxial stack;
forming a second epitaxial stack over the middle semiconductor layer, the second epitaxial stack comprising a second sacrificial layer and a second channel layer over the second sacrificial layer;
etching a recess in the first and second epitaxial stacks and the middle semiconductor layer;
removing the middle semiconductor layer such that a space is between the first and second epitaxial stacks;
after removing the middle semiconductor layer, forming a middle dielectric layer in the space between the first and second epitaxial stacks;
performing a first ion implantation process to form a first lightly doped region adjoining the middle dielectric layer and the first channel layer;
after performing the first ion implantation process, performing a second ion implantation process to form a second lightly doped region adjoining the middle dielectric layer and the second channel layer;
forming a first source/drain epitaxial feature in the recess and adjoining the first lightly doped region;
forming a second source/drain epitaxial feature in the recess and adjoining the second lightly doped region; and
replacing the first sacrificial layer and the second sacrificial layer with a gate structure.
17 . The method of claim 16 , wherein the second lightly doped region is formed in the second channel layer and the middle dielectric layer.
18 . The method of claim 16 , wherein the first lightly doped region is formed in the first channel layer and the middle dielectric layer.
19 . The method of claim 16 , wherein a tilt angle of the second ion implantation process is greater than a tilt angle of the first ion implantation process.
20 . The method of claim 16 , further comprising:
depositing a semiconductor layer into the recess prior to the first ion implantation process, wherein the semiconductor layer has a tapered sidewall facing away from the first channel layer.