Metal oxide semiconductor having epitaxial source drain regions and a method of manufacturing same using dummy gate process
A semiconductor device in which sufficient stress can be applied to a channel region due to lattice constant differences.
1 . A method for manufacturing a semiconductor device, the method comprising:
forming a gate insulating film above a silicon-based substrate;
forming a first Ti-N film above the gate insulating film, the first Ti-N film at least including titanium (Ti) and nitrogen (N);
forming a dummy gate electrode above the first Ti-N film;
forming a first insulating film that is located at least in part on opposite sides of the dummy gate electrode;
forming a first recess region by partially removing the silicon-based substrate through recess etching;
epitaxially growing, on a surface of the first recess region, a source/drain material that includes silicon and an atom having a lattice constant different from a lattice constant of silicon;
forming a second insulating film that is located at least in part over sides of the first insulating film;
forming a second recess region by removing a portion of the dummy gate electrode; and
forming a gate electrode in the second recess region above the gate insulating film.
2 . The method according to claim 1 , wherein the gate insulating film is formed of a material comprising a metal oxide, a metal silicate, a metal oxynitride, or a nitrided metal silicate, wherein the material includes at least one of hafnium (Hf), lanthanum (La), aluminum (Al), zirconium (Zr), or tantalum (Ta).
3 . The method according to claim 1 , wherein a portion of the gate insulating film is located between the gate electrode and the first insulating film.
4 . The method according to claim 1 , wherein the first insulating film is an offset spacer and the second insulating film is a sidewall film.
5 . The method according to claim 1 , further comprising:
forming a refractory metal film across an entire surface of the silicon-based substrate, including on mixed crystal layers, in such a manner as to cover the dummy gate electrode, for which a hard mask and sidewalls have been provided, and wherein the refractory metal film includes cobalt (Co), nickel (Ni), platinum (Pt), or a compound of Co, Ni, and Pt.
6 . The method according to claim 1 , further comprising:
forming a diffusion extension region in the silicon-based substrate such that it extends between the source/drain material and a region below the dummy gate electrode.
7 . The method according to claim 1 , wherein the gate insulating film is located at least in part between the gate electrode and the silicon-based substrate.
8 . The method according to claim 1 , further comprising:
forming a third insulating film that is located at least in part on opposite sides of the gate electrode and of the first insulating film.
9 . The method according to claim 8 , further comprising:
forming a fourth insulating film above the third insulating film.
10 . The method according to claim 8 , wherein the second insulating film is located at least in part between the first insulating film and the third insulating film.
11 . The method according to claim 1 , wherein material of the source/drain material includes a mixed crystal layer in first recess regions of a surface of the silicon-based substrate, the first recess regions being at both sides of the gate electrode, the mixed crystal layer including at least silicon (Si) and germanium (Ge).
12 . The method according to claim 1 , further comprising:
forming a fourth insulating film contacting at least a portion of a top surface of the gate electrode.
13 . The method according to claim 1 , wherein the first insulating film does not contact a top surface of the gate electrode.
14 . The method according to claim 1 , wherein the first insulating film is located at least in part between the gate electrode and the second insulating film.
15 . The method according to claim 1 , wherein the second insulating film covers the first insulating film.
16 . The method according to claim 1 , wherein the gate electrode comprises at least one metal material.
17 . The method according to claim 1 , further comprising:
forming a shallow-junction extension region above the silicon-based substrate that extends into a channel region underneath the gate electrode.
18 . The method according to claim 1 , further comprising:
forming a silicon-based insulating film located at least in part between the gate insulating film and the silicon-based substrate.
19 . The method according to claim 1 , wherein the first Ti-N film is in contact with the gate insulating film.
20 . The method according to claim 1 , wherein the first Ti-N film is a cap film.
21 . The method according to claim 1 , further comprising:
forming a second Ti-N film located at least in part between the gate electrode and the gate insulating film, the second Ti-N film including at least the Ti and the N.
22 . The method according to claim 21 , wherein the second Ti-N film is in contact with the gate electrode.
23 . The method according to claim 21 , wherein the second Ti-N film is an adhesion layer.
24 . The method according to claim 1 , wherein at least a portion of the first insulating film is in contact with material of the source/drain material.
25 . The method according to claim 1 , further comprising:
forming a first Ta film located at least in part between the gate electrode and the gate insulating film, the first Ta film including at least the Ta.
26 . The method according to claim 25 , wherein the first Ta film further includes N.
27 . The method according to claim 25 , wherein the first Ti-N film is an adhesion layer.
28 . The method according to claim 25 , wherein the first Ti-N film is in contact with the first insulating film.