Integrated circuit structures having raised epitaxy on channel transistor
Structures having raised epitaxy on channel structure transistors are described. In an example, an integrated circuit structure includes a channel structure having multi-layer epitaxial source or drain structures thereon, the multi-layer epitaxial source or drain structures having a recess extending there through. A gate dielectric layer is on a bottom and along sides of the recess and laterally surrounded by the epitaxial source or drain structures. A gate electrode is on and laterally surrounded by the gate dielectric layer. The gate electrode has an uppermost surface below an uppermost surface of the gate dielectric layer.
1 . An integrated circuit structure, comprising:
a channel structure having multi-layer epitaxial source or drain structures on a top surface thereof, the multi-layer epitaxial source or drain structures having an opening extending there through;
a gate dielectric layer on a bottom and along sides of the opening and laterally surrounded by the epitaxial source or drain structures; and
a gate electrode on and laterally surrounded by the gate dielectric layer, the gate electrode having an uppermost surface below an uppermost surface of the gate dielectric layer.
2 . The integrated circuit structure of claim 1 , wherein the channel structure is a fin-based channel structure.
3 . The integrated circuit structure of claim 1 , wherein the channel structure is a nanowire-based channel structure.
4 . The integrated circuit structure of claim 1 , wherein the channel structure comprises In, Ga and As, or comprises In and As.
5 . The integrated circuit structure of claim 1 , wherein the multi-layer epitaxial source or drain structures comprise a layer comprising In and P or comprising In, Ga, an As.
6 . An integrated circuit structure, comprising:
a front-side structure comprising:
a device layer having a plurality of fin-based transistors; and
a plurality of metallization layers above the fin-based transistors of the device layer;
a backside structure below the fin-based transistors of the device layer, the backside structure including a ground metal line; and
one or more raised epitaxy on channel structure transistors between the fin-based transistors of the device layer and the ground metal line of the backside structure, wherein individual ones of the one or more raised epitaxy on channel structure transistors comprise a channel structure having multi-layer epitaxial source or drain structures on a top surface thereof, the multi-layer epitaxial source or drain structures having an opening extending there through.
7 . The integrated circuit structure of claim 6 , wherein the one or more raised epitaxy on channel structure transistors are fin-based or nanowire-based raised epitaxy on channel structure transistors.
8 . The integrated circuit structure of claim 6 , wherein each of the one or more raised epitaxy on channel structure transistors is a keeper or power gate.
9 . The integrated circuit structure of claim 6 , wherein the ground metal line of the backside structure is for power delivery.
10 . The integrated circuit structure of claim 6 , wherein the one or more raised epitaxy on channel structure transistors are included in the front-side structure.
11 . A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a channel structure having multi-layer epitaxial source or drain structures on a top surface thereof, the multi-layer epitaxial source or drain structures having an opening extending there through;
a gate dielectric layer on a bottom and along sides of the opening and laterally surrounded by the epitaxial source or drain structures; and
a gate electrode on and laterally surrounded by the gate dielectric layer, the gate electrode having an uppermost surface below an uppermost surface of the gate dielectric layer.
12 . The computing device of claim 11 , further comprising:
a memory coupled to the board.
13 . The computing device of claim 11 , further comprising:
a communication chip coupled to the board.
14 . The computing device of claim 11 , wherein the component is a packaged integrated circuit die.
15 . The computing device of claim 11 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.
16 . A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a front-side structure comprising:
a device layer having a plurality of fin-based transistors; and
a plurality of metallization layers above the fin-based transistors of the device layer;
a backside structure below the fin-based transistors of the device layer, the backside structure including a ground metal line; and
one or more raised epitaxy on channel structure transistors between the fin-based transistors of the device layer and the ground metal line of the backside structure, wherein individual ones of the one or more raised epitaxy on channel structure transistors comprise a channel structure having multi-layer epitaxial source or drain structures on a top surface thereof, the multi-layer epitaxial source or drain structures having an opening extending there through.
17 . The computing device of claim 16 , further comprising:
a memory coupled to the board.
18 . The computing device of claim 16 , further comprising:
a communication chip coupled to the board.
19 . The computing device of claim 16 , wherein the component is a packaged integrated circuit die.
20 . The computing device of claim 16 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.