Silicon carbide semiconductor device
A SiC device includes an n-type semiconductor layer provided on a SiC substrate; a p-type first well region is provided in an upper layer part of the semiconductor layer; an n-type first impurity region is provided in an upper layer part of the first well region; a p-type first well contact region is provided in the upper layer part of the first well region and having a side surface joined to the first impurity region; a first contact electrically connected to the first impurity region and the first well contact region and electrically connected to a first main electrode provided over the semiconductor layer; a second well region separated from the first well region; a p-type second well contact region is provided in an upper layer part of the second well region; and a second contact electrically connected to the second well contact region.
1 . A silicon carbide semiconductor device in which a main current flows in a thickness direction of a silicon carbide substrate, comprising:
a semiconductor layer of a first conductivity type provided on a first main surface of the silicon carbide substrate;
a first well region of a second conductivity type provided in an upper layer part of the semiconductor layer and having a stripe shape extending in a first direction;
a first impurity region of the first conductivity type provided in an upper layer part of the first well region;
at least one first well contact region of the second conductivity type provided in the upper layer part of the first well region and having a side surface joined to the first impurity region;
a first contact electrically connected to the first impurity region and the at least one first well contact region and electrically connected to a first main electrode provided over the semiconductor layer;
a second well region of the second conductivity type having a stripe shape separated from the first well region in a second direction perpendicular to the first direction, extending in the first direction, and having no impurity region of the first conductivity type inside the second well region;
at least one second well contact region of the second conductivity type provided in an upper layer part of the second well region;
a second contact electrically connected to the at least one second well contact region and electrically connected to the first main electrode provided over the semiconductor layer; and
a second main electrode provided on a second main surface of the silicon carbide substrate on an opposite side to the first main surface, wherein
in an area in which the first well region and the second well region are adjacent to each other, a gate electrode is provided across a gate insulating film provided on a peripheral portion of the first impurity region, on the first well region, on the semiconductor layer, and on a peripheral portion of the second well region.
2 . The silicon carbide semiconductor device according to claim 1 , wherein
the at least one second well contact region is absent in a part without the second contact on the second well region.
3 . The silicon carbide semiconductor device according to claim 1 , wherein
the at least one first well contact region includes a plurality of the first well contact regions separated from each other in the first direction and the at least one second well contact region includes a plurality of the second well contact regions separated from each other in the first direction, and
an interval between the second well contact regions adjacent to each other is greater than an interval between the first well contact regions adjacent to each other.
4 . The silicon carbide semiconductor device according to claim 1 , further comprising:
a third impurity region of the first conductivity type provided at least directly under the second well region, having a higher impurity concentration than the semiconductor layer, and having a lower impurity concentration than the second well region.
5 . The silicon carbide semiconductor device according to claim 1 , wherein
in an area in which the first well region and the second well region are adjacent to each other and in which the second contact is absent, the gate electrode is separated into a first part extending from over the semiconductor layer to the first well region and the peripheral portion of the first impurity region and a second part extending from over the semiconductor layer to the second well region.
6 . The silicon carbide semiconductor device according to claim 1 , wherein
the first well region and the second well region are formed at different forming ratios per unit area in a plan view.
7 . The silicon carbide semiconductor device according to claim 1 , wherein
the first impurity region is formed discontinuously in the first direction.
8 . The silicon carbide semiconductor device according to claim 1 , wherein
a contact resistance in the second contact with the at least one second well contact region is higher than a contact resistance in the first contact with the at least one first well contact region.
9 . The silicon carbide semiconductor device according to claim 1 , wherein
the at least one first well contact region is provided in a stripe shape in the first direction, and
the at least one second well contact region is provided locally.
10 . A silicon carbide semiconductor device in which a main current flows in a thickness direction of a silicon carbide substrate, comprising:
a semiconductor layer of a first conductivity type provided on a first main surface of the silicon carbide substrate;
a first well region of a second conductivity type provided in an upper layer part of the semiconductor layer and having a stripe shape extending in a first direction;
a first impurity region of the first conductivity type provided in an upper layer part of the first well region;
at least one first well contact region of the second conductivity type provided in the upper layer part of the first well region and having a side surface joined to the first impurity region;
a first contact electrically connected to the first impurity region and the at least one first well contact region and electrically connected to a first main electrode provided over the semiconductor layer;
a second well region of the second conductivity type having a stripe shape separated from the first well region in a second direction perpendicular to the first direction and extending in the first direction;
at least one second well contact region of the second conductivity type provided in an upper layer part of the second well region;
a second impurity region of the first conductivity type provided in the upper layer part of the second well region, joined to a side surface of the at least one second well contact region, and having an area smaller than that of the first impurity region in a plan view;
a second contact electrically connected to the at least one second well contact region and electrically connected to the first main electrode provided over the semiconductor layer; and
a second main electrode provided on a second main surface of the silicon carbide substrate on an opposite side to the first main surface, wherein
in an area in which the first well region and the second well region are adjacent to each other, a gate electrode is provided across a gate insulating film provided on a peripheral portion of the first impurity region, on the first well region, on the semiconductor layer, and on a peripheral portion of the second well region.
11 . The silicon carbide semiconductor device according to claim 10 , wherein
the at least one second well contact region is absent in a part without the second contact on the second well region.
12 . The silicon carbide semiconductor device according to claim 10 , wherein
the at least one first well contact region includes a plurality of the first well contact regions separated from each other in the first direction and the at least one second well contact region includes a plurality of the second well contact regions separated from each other in the first direction, and
an interval between the second well contact regions adjacent to each other is greater than an interval between the first well contact regions adjacent to each other.
13 . The silicon carbide semiconductor device according to claim 10 , further comprising:
a third impurity region of the first conductivity type provided at least directly under the second well region, having a higher impurity concentration than the semiconductor layer, and having a lower impurity concentration than the second well region.
14 . The silicon carbide semiconductor device according to claim 10 , wherein
in an area in which the first well region and the second well region are adjacent to each other and in which the second contact is absent, the gate electrode is separated into a first part extending from over the semiconductor layer to the first well region and the peripheral portion of the first impurity region and a second part extending from over the semiconductor layer to the second well region.
15 . The silicon carbide semiconductor device according to claim 10 , wherein
the first well region and the second well region are formed at different forming ratios per unit area in a plan view.
16 . The silicon carbide semiconductor device according to claim 10 , wherein
the first impurity region is formed discontinuously in the first direction.
17 . The silicon carbide semiconductor device according to claim 10 , wherein
a contact resistance in the second contact with the at least one second well contact region is higher than a contact resistance in the first contact with the at least one first well contact region.
18 . The silicon carbide semiconductor device according to claim 10 , wherein
the at least one first well contact region is provided in a stripe shape in the first direction, and
the at least one second well contact region is provided locally.