LDMOS device and method of fabrication of same
An LDMOS device includes a semiconductor substrate with an epitaxial layer that comprises a body region and a drain drift region. A drain region is formed in the drain drift region and a source region is formed in the body region. A gate shield may be formed over a gate shield dielectric layer disposed over a gate electrode, the gate shield having a variable length and tied to the source that is provided with a body connection via a deep trench contact.
1 . A semiconductor device, comprising:
a semiconductor substrate including an epitaxial layer, the epitaxial layer including a body region having a first conductivity type and a drain drift region having a second, opposite, conductivity type;
a gate dielectric layer over the body region and extending over a junction between the body region and the drain drift region;
a gate electrode over the gate dielectric layer;
a drain region having the second conductivity type in the drain drift region;
a field relief dielectric layer over the drain drift region, the field relief dielectric layer extending from the gate dielectric layer toward the drain region;
a source region having the second conductivity type in the body region, the source region formed proximate to the gate electrode;
a gate shield dielectric layer over the gate electrode; and
a gate shield over the gate shield dielectric layer, the gate shield coupled to a trench contact electrically contacting the source region and extending over at least a portion of the gate electrode.
2 . The semiconductor device as recited in claim 1 , wherein the trench contact has a depth of about 0.15 μm to 0.5 μm into the body region.
3 . The semiconductor device as recited in claim 1 , further comprising a backgate region underlying the source region, the backgate region including a dopant species of the first conductivity type, the trench contact extending into the backgate region.
4 . The semiconductor device as recited in claim 1 , wherein the gate shield dielectric layer has a thickness of about 0.1 μm to 0.5 μm.
5 . The semiconductor device as recited in claim 1 , wherein the gate shield comprises a metal layer having a thickness of about 20 nm to 80 nm.
6 . The semiconductor device as recited in claim 1 , further comprising a metal silicide layer over the trench contact, wherein the gate shield touches the metal silicide layer.
7 . The semiconductor device as recited in claim 6 , wherein the silicide layer comprises titanium and the gate shield comprises aluminum.
8 . The semiconductor device as recited in claim 5 , wherein the gate shield has a length equal to a length of the gate electrode plus or minus of about 0.1 μm to 0.2 μm.
9 . The semiconductor device as recited in claim 1 , wherein the field relief dielectric layer comprises a local oxidation of silicon (LOCOS) structure having a bird's beak terminating adjacent to the drain region.
10 . The semiconductor device as recited in claim 1 , further comprising a sidewall spacer disposed on a sidewall of the gate electrode proximate to the source region.
11 . A method of fabricating a semiconductor device, comprising:
forming a body region and a drain drift region in an epitaxial layer of a semiconductor substrate, the body region having a first conductivity type and the drain drift region having a second, opposite, conductivity type;
forming a gate dielectric layer over the body region, the gate dielectric layer extending over a junction between the body region and the drain drift region;
forming a field relief dielectric layer over the drain drift region, the field relief dielectric layer extending from the gate dielectric layer and terminating in a bird's beak;
forming a gate electrode over the gate dielectric layer;
forming a drain region having the second conductivity type in the drain drift region, the drain region formed proximate to the bird's beak;
forming a source region having the second conductivity type in the body region, the source region formed proximate to the gate electrode;
forming a gate shield dielectric layer over the gate electrode; and
forming a gate shield over the gate shield dielectric layer, the gate shield coupled to a trench contact electrically contacting the source region and extending over at least a portion of the gate electrode.
12 . The method as recited in claim 11 , wherein the trench contact is formed to have a depth of about 0.15 μm to 0.5 μm into the body region.
13 . The method as recited in claim 11 , further comprising:
forming a backgate region underlying the source region, the backgate region including with a dopant species of the first conductivity type; and
forming the trench contact extending into the backgate region.
14 . The method as recited in claim 13 , further comprising forming a DWELL region in the body region, the DWELL region surrounding the source region.
15 . The method as recited in claim 11 , wherein the gate shield dielectric layer is formed to have a thickness of about 0.2 μm to 0.5 μm.
16 . The method as recited in claim 11 , wherein the gate shield is formed of a metal layer having a thickness of about 20 nm to 80 nm.
17 . The method as recited in claim 11 , further comprising forming a metal silicide layer over the trench contact, and the gate shield touches the metal silicide layer.
18 . The method as recited in claim 17 , wherein the silicide layer comprises titanium and the gate shield comprises aluminum.
19 . The method as recited in claim 16 , wherein the gate shield is formed to have a length equal to a length of the gate electrode plus or minus of about 0.1 μm to 0.2 μm.
20 . The method as recited in claim 11 , wherein the field relief dielectric layer is formed in a local oxidation of silicon (LOCOS) process creating the bird's beak adjacent to the drain region.
21 . The method as recited in claim 11 , further comprising forming a sidewall spacer on a sidewall of the gate electrode proximate to the source region, the sidewall spacer extending to the trench contact.
22 . An integrated circuit, comprising:
a semiconductor substrate including an epitaxial layer, the epitaxial layer including a body region having a first conductivity type and a drain drift region having a second, opposite, conductivity type;
a gate dielectric layer over the body region and extending over a junction between the body region and the drain drift region;
a gate electrode over the gate dielectric layer;
a drain region having the second conductivity type in the drain drift region;
a field relief dielectric layer over the drain drift region, the field relief dielectric layer extending from the gate dielectric layer toward the drain region;
a source region having the second conductivity type in the body region;
a trench having a sidewall along the source region and extending below a junction between the source region and a body contact region; and
a gate shield that extends along the sidewall into the trench and over at least a portion of the gate electrode.
23 . An electronic device, comprising:
a source region and a drain region spaced apart along a semiconductor layer and having a first conductivity type;
a body region having an opposite second conductivity type extending from under the source region toward the drain region;
a dielectric layer on the semiconductor layer that extends between the source region and the drain region;
an electrode extending between the source region and the drain region on the dielectric layer;
a trench having a sidewall along the source region and extending below a junction between the source region and the body region; and
a conductive layer that extends along the sidewall and over the electrode.
24 . The electronic device of claim 23 , further comprising a doped region having the first conductivity type that extends from the drain region toward the source region, wherein the conductive layer extends over the doped region.
25 . The electronic device of claim 23 , wherein the dielectric layer includes a first segment having a first thickness extending between the source and the drain, and a second segment having a greater second thickness extending from the first segment toward the drain, and the conductive layer extends over the second segment of the dielectric layer.
26 . The electronic device of claim 25 , wherein the segment includes a local oxidation of silicon (LOCOS) structure.
27 . A method of forming an electronic device, comprising:
forming a source region and a drain region spaced apart along a semiconductor layer and having a first conductivity type;
forming a body region having an opposite second conductivity type extending from under the source region toward the drain region;
forming a dielectric layer on the semiconductor layer that extends between the source region and the drain region;
forming an electrode extending between the source region and the drain region on the dielectric layer;
forming a trench having a sidewall along the source region and extending below a junction between the source region and the body region; and
forming a conductive layer that extends along the sidewall and over the electrode.
28 . The method of claim 27 , further comprising forming a doped region having the first conductivity type that extends from the drain region toward the source region, wherein the conductive layer extends over the doped region.
29 . The method of claim 27 , wherein the dielectric layer includes a first segment having a first thickness extending between the source and the drain, and a second segment having a greater second thickness extending from the first segment toward the drain, and the conductive layer extends over the second segment of the dielectric layer.
30 . The method of claim 29 , wherein the segment includes a local oxidation of silicon (LOCOS) structure.