Conductive via bar self-aligned to gate end
Conductive via bars self-aligned to gate ends are described. In an example, an integrated circuit structure includes a plurality of gate structures. The integrated circuit structure also includes a plurality of dielectric spacers, a corresponding one of the plurality of dielectric spacers laterally surrounding a corresponding one of the plurality of gate structures. A plurality of conductive trench contact structures is alternating with the plurality of gate structures. A conductive via bar is along ends of the plurality of gate structures and ends of the plurality of conductive trench contact structures, wherein the plurality of dielectric spacers is between the ends of the plurality of gate structures and the conductive via bar.
1 . An integrated circuit structure, comprising:
a plurality of gate structures;
a plurality of dielectric spacers, a corresponding one of the plurality of dielectric spacers laterally surrounding a corresponding one of the plurality of gate structures;
a plurality of conductive trench contact structures alternating with the plurality of gate structures; and
a conductive via bar along ends of the plurality of gate structures and ends of the plurality of conductive trench contact structures, wherein the plurality of dielectric spacers is between the ends of the plurality of gate structures and the conductive via bar, and wherein the conductive via bar has an uppermost surface at a same level as an uppermost surface of the plurality of dielectric spacers in a cross-sectional view.
2 . The integrated circuit structure of claim 1 , wherein the plurality of dielectric spacers has an uppermost surface co-planar with an uppermost surface of the plurality of gate structures and co-planar with an uppermost surface of the plurality of conductive trench contact structures and co-planar with an uppermost surface of the conductive via bar.
3 . The integrated circuit structure of claim 1 , wherein one or more of the plurality of conductive trench contact structures is separated from the conductive via bar by a corresponding dielectric plug.
4 . The integrated circuit structure of claim 1 , wherein the plurality of gate structures is over one or more sub-fins, and the conductive via bar has a bottommost surface above a top surface of the one or more sub-fins.
5 . The integrated circuit structure of claim 1 , wherein the plurality of gate structures is over one or more sub-fins, and the conductive via bar has a bottommost surface below a top surface of the one or more sub-fins.
6 . The integrated circuit structure of claim 1 , wherein the plurality of gate structures is over one or more stacks of semiconductor nanowires.
7 . The integrated circuit structure of claim 1 , wherein the plurality of gate structures is over one or more stacks of semiconductor nanoribbons.
8 . The integrated circuit structure of claim 1 , wherein the plurality of gate structures is over one or more semiconductor fins.
9 . A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a plurality of gate structures;
a plurality of dielectric spacers, a corresponding one of the plurality of dielectric spacers laterally surrounding a corresponding one of the plurality of gate structures;
a plurality of conductive trench contact structures alternating with the plurality of gate structures; and
a conductive via bar along ends of the plurality of gate structures and ends of the plurality of conductive trench contact structures, wherein the plurality of dielectric spacers is between the ends of the plurality of gate structures and the conductive via bar, and wherein the conductive via bar has an uppermost surface at a same level as an uppermost surface of the plurality of dielectric spacers in a cross-sectional view.
10 . The computing device of claim 9 , further comprising:
a memory coupled to the board.
11 . The computing device of claim 9 , further comprising:
a communication chip coupled to the board.
12 . The computing device of claim 9 , further comprising:
a camera coupled to the board.
13 . The computing device of claim 9 , wherein the component is a packaged integrated circuit die.
14 . A method of fabricating an integrated circuit structure, the method comprising:
forming a plurality of gate structures;
forming a plurality of dielectric spacers, a corresponding one of the plurality of dielectric spacers laterally surrounding a corresponding one of the plurality of gate structures;
forming a plurality of conductive trench contact structures alternating with the plurality of gate structures; and
forming a conductive via bar along ends of the plurality of gate structures and ends of the plurality of conductive trench contact structures, wherein the plurality of dielectric spacers is between the ends of the plurality of gate structures and the conductive via bar, and wherein the conductive via bar has an uppermost surface at a same level as an uppermost surface of the plurality of dielectric spacers in a cross-sectional view.
15 . The method of claim 14 , wherein the plurality of dielectric spacers has an uppermost surface co-planar with an uppermost surface of the plurality of gate structures and co-planar with an uppermost surface of the plurality of conductive trench contact structures and co-planar with an uppermost surface of the conductive via bar.
16 . The method of claim 14 , wherein one or more of the plurality of conductive trench contact structures is separated from the conductive via bar by a corresponding dielectric plug.
17 . The method of claim 14 , wherein the plurality of gate structures is over one or more sub-fins, and the conductive via bar has a bottommost surface above a top surface of the one or more sub-fins.
18 . The method of claim 14 , wherein the plurality of gate structures is over one or more sub-fins, and the conductive via bar has a bottommost surface below a top surface of the one or more sub-fins.
19 . The method of claim 14 , wherein the plurality of gate structures is over one or more stacks of semiconductor nanowires.
20 . The method of claim 14 , wherein the plurality of gate structures is over one or more stacks of semiconductor nanoribbons.
21 . The method of claim 14 , wherein the plurality of gate structures is over one or more semiconductor fins.