IP Library Granted Patent US 12672335
Granted Patent B2
US 12672335 · App. 18/770,393 · Granted Jun 30, 2026

Backside contact structures for semiconductor devices

Inventors: Chia-Hung Chu (Taipei City, TW); Tsungyu Hung (Hsinchu City, TW); Hsu-Kai Chang (Hsinchu, TW); Ding-Kang Shih (New Taipei City, TW); Keng-Chu Lin (Chao-Chou, TW); Pang-Yen Tsai (Jhu-bei City, TW); Sung-Li Wang (Zhubei City, TW); Shuen-Shin Liang (Hsinchu County, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H10D64/258H10D30/6735H10D64/01H10D64/0112
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Quick Facts
Patent No.
US 12672335
App. No.
18/770,393
Granted
Jun 30, 2026
Kind
B2
Abstract

The present disclosure describes a method to form a semiconductor device with backside contact structures. The method includes forming a semiconductor device on a first side of a substrate. The semiconductor device includes a source/drain (S/D) region. The method further includes etching a portion of the S/D region on a second side of the substrate to form an opening and forming an epitaxial contact structure on the S/D region in the opening. The second side is opposite to the first side. The epitaxial contact structure includes a first portion in contact with the S/D region in the opening and a second portion on the first portion. A width of the second portion is larger than the first portion.

Claims (53)

1 . A method, comprising:

forming a semiconductor device on a first side of a substrate, wherein the semiconductor device comprises a source/drain (S/D) region;

removing a portion of the S/D region on a second side of the substrate opposite to the first side;

epitaxially growing a contact structure with a semiconductor material on the S/D region on the second side of the substrate; and

forming a metal silicide layer on the contact structure.

2 . The method of claim 1 , wherein the epitaxially growing the contact structure comprises growing the contact structure with a rounded surface.

3 . The method of claim 1 , wherein the epitaxially growing the contact structure comprises growing the contact structure with one or more facets.

4 . The method of claim 1 , wherein the contact structure comprises a first portion in contact with the S/D region and a second portion on the first portion, a width of the second portion being greater than a width of the first portion.

5 . The method of claim 1 , wherein the epitaxially growing the contact structure comprises growing the contact structure at a temperature ranging from about 350° C. to about 450° C.

6 . The method of claim 1 , wherein the epitaxially growing the contact structure comprises growing the contact structure with an active dopant at a concentration higher than about 1×10 21 cm −3 .

7 . The method of claim 1 , further comprising:

forming an additional semiconductor device on the first side of the substrate, wherein the additional semiconductor device comprises an additional S/D region with a different type of dopant from the S/D region;

etching a portion of the additional S/D region on the second side of the substrate; and

blocking the additional S/D region while epitaxially growing the contact structure on the S/D region.

8 . The method of claim 7 , wherein blocking the additional S/D region comprises:

forming a mask layer on the additional S/D region before epitaxially growing the contact structure; and

removing the mask layer after epitaxially growing the contact structure.

9 . The method of claim 7 , further comprising:

forming the metal silicide layer on the additional S/D region; and

forming a metal contact on the metal silicide layer.

10 . The method of claim 7 , further comprising:

selectively forming the metal silicide layer on the contact structure;

forming a second metal silicide layer on the metal silicide layer and the additional S/D region, wherein the second metal silicide layer comprises a metal different from that of the metal silicide layer; and

forming a metal contact on the second metal silicide layer.

11 . The method of claim 1 , further comprising:

forming a first power rail structure on the first side of the substrate and connected to a gate structure of the semiconductor device; and

forming a second power rail structure on the second side of the substrate and connected to the S/D region of the semiconductor device.

12 . A method, comprising:

forming first and second semiconductor devices on a first side of a substrate, wherein the first semiconductor device comprises a first source/drain (S/D) region and the second semiconductor device comprises a second S/D region;

removing a portion of the first S/D region and a portion of the second S/D region on a second side of the substrate opposite to the first side;

selectively forming a first metal silicide layer on the second S/D region; and

forming a second metal silicide layer on the first metal silicide layer and on the first S/D region, wherein the second metal silicide layer comprises a metal different from that of the first metal silicide layer.

13 . The method of claim 12 , further comprising:

forming a barrier layer on the second side of the substrate before selectively forming the first metal silicide layer;

forming a metal contact on the second metal silicide layer; and

forming a power rail structure on the second metal silicide layer.

14 . The method of claim 13 , wherein the forming the barrier layer comprises:

depositing a conformal barrier layer on the second side of the substrate;

removing a portion of the conformal barrier layer in contact with the first and second S/D regions.

15 . The method of claim 12 , wherein the selectively forming the first metal silicide layer comprises forming the first metal silicide layer at a temperature below about 450° C.

16 . The method of claim 12 , wherein the selectively forming the first metal silicide layer comprises forming the first metal silicide layer with a metal precursor including at least one of nickel, cobalt, and ruthenium.

17 . A semiconductor device, comprising:

a stack of semiconductor layers on a first side of a substrate;

a gate structure wrapped around the stack of semiconductor layers;

a source/drain (S/D) region in contact with the stack of semiconductor layers;

a contact structure in contact with the S/D region on a second side of the substrate, wherein:

the contact structure comprises a semiconductor material;

the contact structure has a convex surface extending into the S/D region; and

the second side is opposite to the first side; and

a metal silicide layer on the contact structure.

18 . The semiconductor device of claim 17 , further comprising a second metal silicide layer on the metal silicide layer, wherein the second metal silicide layer comprises a metal different from that of the metal silicide layer.

19 . The semiconductor device of claim 17 , wherein the contact structure comprises a first portion on the S/D region and a second portion on the first portion, a width of the second portion being greater than a width of the first portion.

20 . The semiconductor device of claim 19 , wherein a ratio of the width of the second portion to the width of the first portion ranges from about 1.1 to about 3.