IP Library › Granted Patent US 12,672,338

Granted Patent B2

US 12,672,338 · App. 18/323,416 · Granted Jun 30, 2026

Semiconductor device having NMOS transistors and channels of PMOS transistors formed of silicon/silicon germanium/silicon wherein silicon germanium not in contact with silicon oxide

Inventor: Young Gwang Yoon (Gyeonggi-do, KR)

Assignee: SK hynix Inc.

H10D84/038 H10D84/0167 H10D84/017 H10D84/0181 H10D84/856

View Patent ↗

Loading inventors, assignments & file history…

Monitor This Case

Get email alerts when status or documents change.

Order Certified Copies

Most orders are placed with the USPTO same day — all within 24 business hours.

Order via The Patent Place →

Pre-filled with this patent's details

Quick Facts

Patent No.: US 12,672,338
App. No.: 18/323,416
Granted: Jun 30, 2026
Kind: B2

External Links

USPTO Patent Center↗ Full Patent PDF↗

Abstract

A semiconductor device includes an NMOS transistor structure formed over an NMOS area of a substrate; and a PMOS transistor structure formed over a PMOS area of the substrate. The NMOS transistor structure includes NMOS source/drain regions, and NMOS channel patterns and NMOS gate structures alternately and repeatedly stacked between the NMOS source/drain regions. The PMOS transistor structure includes PMOS source/drain regions, and PMOS channel patterns and PMOS gate structures alternately and repeatedly stacked between the PMOS source/drain regions.

Claims (67)

1 . A semiconductor device comprising:

an NMOS transistor structure formed over an NMOS area of a substrate; and

a PMOS transistor structure formed over a PMOS area of the substrate,

wherein the NMOS transistor structure includes:

NMOS source/drain regions formed over the substrate; and

NMOS channel patterns and NMOS gate structures alternately and repeatedly stacked over the substrate between the NMOS source/drain regions in a horizontal direction,

wherein the PMOS transistor structure includes:

PMOS source/drain regions formed over the substrate; and

PMOS channel patterns and PMOS gate structures alternately and repeatedly stacked over the substrate between the PMOS source/drain regions in the horizontal direction,

wherein:

each of the NMOS channel patterns includes a single silicon layer, and

each of the PMOS channel patterns includes a first silicon layer, a second silicon layer, and a silicon germanium layer between the first silicon layer and the second silicon layer,

each of the PMOS gate structures includes a PMOS interfacial insulating layer, a PMOS gate insulating layer, and a PMOS gate electrode,

the PMOS interfacial insulating layer is conformally formed over bottom surface of the first silicon layer and top surface of the second silicon layer, and

wherein the silicon germanium layer is not in contact with a silicon oxide layer.

2 . The semiconductor device of claim 1 , wherein:

the single silicon layer of each of the NMOS channel patterns and the second silicon layer of each of the PMOS channel patterns are positioned at a same level, and

a vertical thickness of the single silicon layer of each of the NMOS channel patterns is smaller than a vertical thickness of the second silicon layer of each of the PMOS channel patterns.

3 . The semiconductor device of claim 1 , wherein:

each of the NMOS gate structures includes an NMOS interfacial insulating layer, an NMOS gate insulating layer, an NMOS gate barrier layer, an NMOS outer gate electrode, and an NMOS inner gate electrode.

4 . The semiconductor device of claim 3 , wherein:

the NMOS interfacial insulating layers and the PMOS interfacial insulating layers include a same material,

the NMOS gate insulating layers and the PMOS gate insulating layers include a same material,

the NMOS gate barrier layers and the PMOS gate electrodes include a same material, and

the NMOS outer gate electrodes include an NMOS work function control metal.

5 . The semiconductor device of claim 3 , wherein:

each of the NMOS interfacial insulating layers is conformally formed over top and bottom surfaces of each of the NMOS channel patterns, inner surfaces of the NMOS source/drain regions, and a first surface of the substrate in the NMOS area,

each of the PMOS interfacial insulating layers is conformally formed over inner surfaces of the PMOS source/drain regions, and a second surface of the substrate in the PMOS area, and

the first surface of the substrate is more recessed than the second surface of the substrate.

6 . The semiconductor device of claim 1 ,

wherein a vertical thickness of each of the NMOS channel patterns is smaller than a vertical thickness of each of the PMOS channel patterns.

7 . The semiconductor device of claim 1 ,

wherein a vertical thickness of each of the NMOS gate structures is greater than a vertical thickness of each of the PMOS gate structures.

8 . The semiconductor device of claim 1 ,

wherein the PMOS interfacial insulating layer includes an oxidized silicon layer formed by oxidizing the bottom surface of the first silicon layer and the top surface of the second silicon layer.

9 . The semiconductor device of claim 1 ,

wherein the silicon germanium layer of each of the PMOS channel patterns are not in contact with the PMOS interfacial insulating layer.

10 . A semiconductor device comprising:

an NMOS transistor structure formed over an NMOS area of a substrate; and

a PMOS transistor structure formed over a PMOS area of the substrate,

wherein the NMOS transistor structure includes:

NMOS source/drain regions formed over the substrate; and

NMOS channel patterns and NMOS gate structures alternately and repeatedly stacked between the NMOS source/drain regions in a horizontal direction,

wherein the PMOS transistor structure includes:

PMOS source/drain regions formed over the substrate; and

PMOS channel patterns and PMOS gate structures alternately and repeatedly stacked between the PMOS source/drain regions in the horizontal direction,

wherein:

each of the PMOS gate structures includes a PMOS interfacial insulating layer, a PMOS gate insulating layer, and a PMOS gate electrode,

wherein:

a vertical thickness of each of the NMOS channel patterns is smaller than a vertical thickness of each of the PMOS channel patterns, and

a vertical thickness of each of the NMOS gate structures is greater than a vertical thickness of each of the PMOS gate structures,

wherein each of the PMOS channel patterns includes a first silicon layer, a second silicon layer, and a silicon germanium layer between the first silicon layer and the second silicon layer, and

wherein the silicon germanium layer is not in contact with a silicon oxide layer.

11 . The semiconductor device of claim 10 , wherein:

each of the NMOS channel patterns includes a single silicon layer.

12 . The semiconductor device of claim 10 , wherein:

the NMOS interfacial insulating layers and the PMOS interfacial insulating layers include an oxidized silicon layer,

the NMOS gate insulating layers and the PMOS gate insulating layers include insulating layers containing hafnium or zirconium,

the NMOS gate barrier layers and the PMOS gate electrodes include titanium nitride, and

the NMOS inner gate electrodes include a metal alloy or metal compound containing aluminum.

13 . The semiconductor device of claim 10 , wherein:

each of the NMOS interfacial insulating layers is conformally formed over top and bottom surfaces of the NMOS channel patterns, inner surfaces of the NMOS source/drain regions, and a first surface of the substrate;

each of the PMOS interfacial insulating layers is conformally formed over top and bottom surfaces of the PMOS channel patterns, inner surfaces of the PMOS source/drain regions, and a second surface of the substrate, and

the first surface of the substrate is more recessed than the second surface of the substrate.

14 . The semiconductor device of claim 10 ,

wherein each of the NMOS gate structures further includes the NMOS outer gate electrode between the NMOS gate barrier layer and the NMOS inner gate electrode rather than each of the PMOS gate structures.