Nanosheet devices and methods of fabricating the same
A semiconductor structure includes a substrate and a stack of p-n junction structures embedded in the substrate. The semiconductor structure includes a semiconductor fin protruding from the substrate. The semiconductor structure includes a pair of source/drain structures disposed in the semiconductor fin. The semiconductor structure includes a gate structure over a channel region of the semiconductor fin and interposed between the pair of source/drain structures.
1 . A semiconductor structure, comprising:
a substrate;
a stack of p-n junction structures embedded in the substrate;
a semiconductor fin protruding from the substrate;
a pair of source/drain structures disposed on respective sides of the semiconductor fin;
a gate structure over a channel region of the semiconductor fin and interposed between the pair of source/drain structures; and
a gate spacer disposed between the gate structure and the pair of source/drain structures, wherein the gate structure extends above a top surface of the gate spacer.
2 . The semiconductor structure of claim 1 , wherein the stack of p-n junction structures includes first portions of the substrate doped with an n-type dopant, the first portions being interleaved with second portions of the substrate doped with a p-type dopant.
3 . The semiconductor structure of claim 2 , wherein the pair of source/drain structures includes a first concentration of the n-type dopant and the first portions of the substrate include a second concentration of the n-type dopant, the second concentration being less than the first concentration.
4 . The semiconductor structure of claim 1 , wherein the substrate includes a region doped with a p-type dopant.
5 . The semiconductor structure of claim 1 , wherein the stack of p-n junction structures each extend laterally over a region corresponding to the pair of source/drain structures in a cascading configuration.
6 . The semiconductor structure of claim 1 , wherein the stack of p-n junction structures each extend along a longitudinal direction of the semiconductor fin and is stacked along a direction perpendicular to a top surface of the substrate.
7 . The semiconductor structure of claim 1 , wherein the stack of p-n junction structures extends from a bottom portion of the gate structure to a depth of about 10 nm to about 100 nm along a direction perpendicular to a top surface of the substrate.
8 . The semiconductor structure of claim 1 , wherein the semiconductor fin includes a plurality of semiconductor layers interleaved with the gate structure.
9 . A semiconductor structure, comprising:
a semiconductor substrate;
a junction structure embedded in the semiconductor substrate, the junction structure including pairs of alternating p-type doped regions and n-type doped regions;
a semiconductor fin protruding from the semiconductor substrate, the semiconductor fin including semiconductor layers stacked along a vertical direction;
a gate structure wrapping around a channel region of each semiconductor layer;
a pair of source/drain structures disposed on respective sides of the gate structure; and
a gate spacer extending above a top surface of the pair of source/drain structures, wherein the gate structure extends above a top surface of the gate spacer.
10 . The semiconductor structure of claim 9 , wherein the n-type doped regions each include an n-type dopant at a first concentration and the pair of source/drain structures each include the n-type dopant at a second concentration that is greater than the first concentration.
11 . The semiconductor structure of claim 9 , wherein the junction structure includes at least three pairs of the alternating p-type doped regions and n-type doped regions.
12 . The semiconductor structure of claim 9 , wherein each of the n-type doped regions includes phosphorous.
13 . The semiconductor structure of claim 9 , wherein each of the alternating p-type doped regions is a portion of the semiconductor substrate.
14 . The semiconductor structure of claim 9 , wherein the pairs of alternating p-type doped regions and n-type doped regions are aligned with the pair of the source/drain structures along the vertical direction.
15 . The semiconductor structure of claim 9 , wherein the junction structure extends from a bottom portion of the gate structure to a depth of about 10 nm to about 100 nm in the semiconductor substrate along the vertical direction.
16 . A semiconductor structure, comprising:
an active gate structure having a first side and a second side opposite the first side, wherein the active gate structure is coupled to a gate contact;
a first dielectric layer disposed on the first side of the active gate structure and a second dielectric layer disposed on the second side of the active gate structure;
a first gate spacer disposed on the first dielectric layer and a second gate spacer disposed on the second dielectric layer;
a source structure disposed on the first gate spacer and a drain structure coupled to the second gate spacer, wherein the source structure is coupled to a source contact and the drain structure is coupled to a drain contact;
a semiconductor fin protruding from a substrate and disposed under the active gate structure, wherein the active gate structure extends above the first gate spacer and the second gate spacer; and
a stack of p-n junction structures embedded in the substrate.
17 . The semiconductor structure of claim 16 , wherein the source structure and the drain structure define a semiconductor fin protruding from a substrate.
18 . The semiconductor structure of claim 16 , wherein the source contact, the gate contact, and the drain contact each comprise a conductive metal disposed over a barrier layer.
19 . The semiconductor structure of claim 16 , further comprising a dielectric structure formed over the active gate structure.
20 . The semiconductor structure of claim 16 , wherein the first dielectric layer comprises a dielectric material different from a dielectric material of the second dielectric layer.