Integrated boot diode with high forward bias capability
A microelectronic device including an integrated boot diode and a depleted mode LDMOS transistor with a charge balance layer isolated from the body region and electrically in contact with a substrate. The connection of the charge balance layer of the depleted mode LDMOS transistor directly to the substrate or ground reference eliminates body diode turn-on from the body of the transistor to the drain which typically happens above approximately 0.7 volts. In addition, the depleted mode LDMOS transistor may separate a source contact from a body contact which allows a negative bias of the body with respect to the source. Typically, the source voltage is limited to approximately 7 volts before parasitic PNP turn on becomes a factor. By negatively biasing the body with respect to the source, the maximum source voltage of the depleted mode LDMOS transistor without PNP parasitic turn-on may be increased to approximately 30 V.
1 . A microelectronic device, comprising:
a semiconductor material of a substrate, the semiconductor material including a body region having a first conductivity type and a drain drift region having a second conductivity type;
a charge balance layer over the drain drift region, the charge balance layer being electrically isolated from the body region and being electrically in contact with the substrate;
a field relief dielectric layer over the drain drift region, the field relief dielectric layer extending from a gate dielectric layer toward a drain region and having a thickness greater than the gate dielectric layer, the gate dielectric layer extending over a junction between the body region and the drain drift region;
a gate electrode over the gate dielectric layer;
a source region having the second conductivity type;
the drain region having the second conductivity type contacting the drain drift region, the drain region having a dopant density at least twice the drain drift region; and
a body contact region having the first conductivity type in direct contact with the body region, the body contact region having a dopant density at least twice the body region.
2 . The microelectronic device of claim 1 , wherein the body contact region is separated from the source region.
3 . The microelectronic device of claim 1 , wherein the charge balance layer is of the first conductivity type.
4 . The microelectronic device of claim 1 , wherein the body contact region has a separate electrical connection from an electrical connection of the source region.
5 . The microelectronic device of claim 1 , wherein a threshold voltage region of the second conductivity type is contacting the source region and the drain drift region.
6 . The microelectronic device of claim 1 , wherein the field relief dielectric layer includes a local oxidation of silicon (LOCOS) layer of dielectric material.
7 . The microelectronic device of claim 1 , wherein the first conductivity type is p-type and the second conductivity type is n-type.
8 . The microelectronic device of claim 1 , wherein the body region, the drain drift region, the charge balance layer, and the gate electrode are elements of a depleted mode laterally diffused metal oxide semiconductor (LDMOS) transistor that is a portion of a high voltage isolation circuit of the microelectronic device.
9 . The microelectronic device of claim 1 , wherein a charge balance layer connection is located between the source region and a junction diode of a high voltage isolation circuit.
10 . The microelectronic device of claim 1 , wherein charge balance layer connections to the substrate are located between a plurality of segments of the source region of a high voltage isolation circuit.