IP Library › Granted Patent US 12672344

Granted Patent B2

US 12672344 · App. 18/317,440 · Granted Jun 30, 2026

Integrated circuit structure and method of forming the same

Inventors: Kam-Tou Sio (Hsinchu, TW); Chih-Liang Chen (Hsinchu, TW); Charles Chew-Yuen Young (Hsinchu, TW); Hui-Zhong Zhuang (Hsinchu, TW); Jiann-Tyng Tzeng (Hsinchu, TW); Yi-Hsun Chiu (Hsinchu, TW)

Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

H10D84/82 H10D84/85 H10D84/90 H10D84/907 H10D89/10 H10D84/0186 H10D84/0191 H10D84/038 H10D84/991

View Patent ↗

Loading inventors, assignments & file history…

Monitor This Case

Get email alerts when status or documents change.

Order Certified Copies

Most orders are placed with the USPTO same day — all within 24 business hours.

Order via The Patent Place →

Pre-filled with this patent's details

Quick Facts

Patent No.: US 12672344
App. No.: 18/317,440
Granted: Jun 30, 2026
Kind: B2

External Links

USPTO Patent Center↗ Full Patent PDF↗

Abstract

A method of forming an integrated circuit structure includes generating a first well layout pattern corresponding to fabricating a first well in the integrated circuit structure. The generating the first well layout pattern includes generating a first layout pattern having a first width, and corresponding to fabricating a first portion of the first well, and generating a second layout pattern having a second width and corresponding to fabricating a second portion of the first well. The method further includes generating a first implant layout pattern having a third width and corresponding to fabricating a first set of implants in the first portion of the first well, generating a second implant layout pattern having a fourth width and corresponding to fabricating a second set of implants in the second portion of the first well, and manufacturing the integrated circuit structure based on the above layout patterns.

Claims (70)

1 . A method of forming an integrated circuit structure, the method comprising:

generating a first well layout pattern corresponding to fabricating a first well in the integrated circuit structure, the first well having a first dopant type, the generating the first well layout pattern comprises:

generating a first layout pattern extending in a first direction and having a first width, the first layout pattern corresponding to fabricating a first portion of the first well; and

generating a second layout pattern extending in the first direction, being adjacent to the first layout pattern, and having a second width greater than the first width, the second layout pattern corresponding to fabricating a second portion of the first well; and

generating a first implant layout pattern extending in the first direction, overlapping the first layout pattern and having a third width greater than the first width, the first implant layout pattern corresponding to fabricating a first set of implants in the first portion of the first well of the integrated circuit structure, each implant of the first set of implants having the first dopant type and being separated from each other in the first direction, and at least one implant of the first set of implants being configured to be coupled to a first supply voltage;

generating a second implant layout pattern extending in the first direction, being adjacent to the first implant layout pattern, being over the second layout pattern and having a fourth width, the second implant layout pattern corresponding to fabricating a second set of implants in the second portion of the first well of the integrated circuit structure, each implant of the second set of implants having a second dopant type and being separated from each other in the first direction;

wherein at least one of the above layout patterns is stored on a non-transitory computer-readable medium, and at least one of the above operations is performed by a hardware processor; and

manufacturing the integrated circuit structure based on at least one of the above layout patterns of the integrated circuit structure.

2 . The method of claim 1 , further comprising:

generating a second well layout pattern extending in the first direction, being adjacent to the second layout pattern, and having a fifth width greater than the first width, the second well layout pattern corresponding to fabricating a second well of the integrated circuit structure, the second well having the second dopant type.

3 . The method of claim 2 , further comprising:

generating a third implant layout pattern extending in the first direction, being over the second well layout pattern and having a sixth width less than the third width or the fourth width, the third implant layout pattern corresponding to fabricating a third set of implants in the second well of the integrated circuit structure, each implant of the third set of implants having the second dopant type and being separated from each other in the first direction, and at least one implant of the third set of implants being configured to be coupled to a second supply voltage different from the first supply voltage,

the second layout pattern being between the first layout pattern and the second well layout pattern, and

the second implant layout pattern being between the first implant layout pattern and the third implant layout pattern.

4 . The method of claim 3 , further comprising:

generating a third well layout pattern extending in the first direction, and being adjacent to the first layout pattern, the third well layout pattern corresponding to fabricating a third well, the third well extending in the first direction, being separated from the first portion of the first well in the first direction, and having the second dopant type.

5 . The method of claim 4 , further comprising:

generating a fourth well layout pattern extending in the first direction, and being adjacent to the first layout pattern, the fourth well layout pattern corresponding to fabricating a fourth well, the fourth well extending in the first direction, being separated from the first portion of the first well in the first direction, and having the second dopant type;

wherein the first portion of the first well layout pattern is between the third well layout pattern and the fourth well layout pattern; and

the first implant layout pattern overlaps the third well layout pattern and the fourth well layout pattern.

6 . The method of claim 4 , further comprising:

generating a fourth implant layout pattern extending in the first direction, being over the third well layout pattern, and adjacent to the third implant layout pattern, the fourth implant layout pattern corresponding to fabricating a fourth set of implants in the third well of the integrated circuit structure, each implant of the fourth set of implants having the first dopant type and being separated from each other in the first direction.

7 . The method of claim 6 , further comprising:

generating a fifth implant layout pattern extending in the first direction, being over the third well layout pattern, and adjacent to the third implant layout pattern, the fourth implant layout pattern corresponding to fabricating a fifth set of implants in the third well of the integrated circuit structure, each implant of the fifth set of implants having the first dopant type and being separated from each other in the first direction,

wherein the third implant layout pattern is between the fourth implant layout pattern and the fifth implant layout pattern.

8 . The method of claim 3 , wherein the generating the first well layout pattern further comprises:

generating a third layout pattern extending in the first direction, and being adjacent to the second layout pattern, the third layout pattern corresponding to fabricating a third portion of the first well, the third portion of the first well having the first dopant type, and being adjacent to the second portion of the first well,

wherein the second implant layout pattern overlaps the third layout pattern.

9 . The method of claim 3 , further comprising:

generating a set of gate layout patterns extending in a second direction and overlapping the first well layout pattern and the second well layout pattern, the set of gate layout patterns corresponding to fabricating a set of gates in the integrated circuit structure, each gate of the set of gates being separated from each other in the first direction, and at least an implant of the second set of implants is between a pair of gates of the set of gates.

10 . A method of forming an integrated circuit structure, the method comprising:

generating a first layout pattern extending in a first direction and having a first width, the first layout pattern corresponding to fabricating a first portion of the first well, and

generating a set of standard cell layout patterns adjacent to the first well layout pattern and the first implant layout pattern, the set of standard cell layout patterns corresponding to fabricating a set of standard cells of the integrated circuit structure, the set of standard cells comprising a set of transistors, and the set of standard cells being arranged in rows and columns,

wherein at least one of the above layout patterns is stored on a non-transitory computer-readable medium, and at least one of the above operations is performed by a hardware processor; and

manufacturing the integrated circuit structure based on at least one of the above layout patterns of the integrated circuit structure.

11 . The method of claim 10 , further comprising:

12 . A method of forming an integrated circuit structure, the method comprising:

generating a first layout pattern extending in a first direction and having a first width, the first layout pattern corresponding to fabricating a first portion of the first well; and

placing a first implant layout pattern over the first layout pattern, the first implant layout pattern extending in the first direction, and having a third width greater than the first width, the first implant layout pattern corresponding to fabricating a first set of implants in the first portion of the first well of the integrated circuit structure, each implant of the first set of implants having the first dopant type and being separated from each other in the first direction, and at least one implant of the first set of implants being configured to be coupled to a first supply voltage;

placing a second implant layout pattern over the second layout pattern, the second implant layout pattern extending in the first direction, being adjacent to the first implant layout pattern, and having a fourth width, the second implant layout pattern corresponding to fabricating a second set of implants in the second portion of the first well of the integrated circuit structure, each implant of the second set of implants having a second dopant type and being separated from each other in the first direction;

wherein at least one of the above layout patterns is stored on a non-transitory computer-readable medium, and at least one of the above operations is performed by a hardware processor; and

manufacturing the integrated circuit structure based on at least one of the above layout patterns of the integrated circuit structure.

13 . The method of claim 12 , further comprising:

14 . The method of claim 13 , further comprising:

the second layout pattern being between the first layout pattern and the second well layout pattern, and

the second implant layout pattern being between the first implant layout pattern and the third implant layout pattern.

15 . The method of claim 14 , further comprising:

16 . The method of claim 15 , further comprising:

wherein the first portion of the first well layout pattern is between the third well layout pattern and the fourth well layout pattern; and

the first implant layout pattern overlaps the third well layout pattern and the fourth well layout pattern.

17 . The method of claim 15 , further comprising:

18 . The method of claim 17 , further comprising:

wherein the third implant layout pattern is between the fourth implant layout pattern and the fifth implant layout pattern.

19 . The method of claim 14 , wherein the generating the first well layout pattern further comprises:

wherein the second implant layout pattern overlaps the third layout pattern.

20 . The method of claim 14 , further comprising: