Semiconductor device and method for forming the same
A semiconductor device includes a first transistor, a second transistor above the first transistor, and an isolation structure. The first transistor includes a first semiconductor channel layer, a first gate structure wrapping around the first semiconductor channel layer, and first source/drain epitaxy structures on opposite ends of the first semiconductor channel layer. The second transistor includes a second semiconductor channel layer, a second gate structure wrapping around the second semiconductor channel layer, and second source/drain epitaxy structures on opposite ends of the second semiconductor channel layer. The isolation structure electrically isolates the first gate structure from the second gate structure, wherein in a top view the isolation structure is adjacent to the second gate structure, and wherein in a first cross-sectional view, the isolation structure wraps around the first semiconductor channel layer.
1 . A semiconductor device, comprising:
a first transistor over a substrate, comprising:
a first semiconductor channel layer;
a first gate structure wrapping around the first semiconductor channel layer; and
first source/drain epitaxy structures on opposite ends of the first semiconductor channel layer;
a second transistor vertically above the first transistor, comprising:
a second semiconductor channel layer;
a second gate structure wrapping around the second semiconductor channel layer; and
second source/drain epitaxy structures on opposite ends of the second semiconductor channel layer; and
an isolation structure electrically isolating the first gate structure from the second gate structure, wherein in a top view the isolation structure is adjacent to the second gate structure, and wherein in a first cross-sectional view, the isolation structure wraps around the first semiconductor channel layer.
2 . The semiconductor device of claim 1 , wherein a top surface of the isolation structure is substantially level with a top surface of the second gate structure, while a bottom surface of the isolation structure is lower than a bottom surface of the second gate structure.
3 . The semiconductor device of claim 1 , wherein the isolation structure has a portion vertically between the first semiconductor channel layer and the substrate, and wherein in a second cross-sectional view perpendicular to the first cross-sectional view, the first gate structure wraps around the portion of the isolation structure.
4 . The semiconductor device of claim 1 , wherein in the first cross-sectional view, the isolation structure is in contact with a sidewall and a bottom surface of the second gate structure.
5 . The semiconductor device of claim 1 , further comprising a bottom gate contact electrically connected to the first gate structure, wherein the isolation structure is laterally between the bottom gate contact and the second gate structure.
6 . The semiconductor device of claim 5 , wherein in the first cross-sectional view, the first gate structure comprises a gate electrode in contact with a bottom surface of the bottom gate contact.
7 . The semiconductor device of claim 5 , wherein a top surface of the bottom gate contact is substantially level with a top surface of the second gate structure, and a bottom surface of the bottom gate contact is lower than a bottom surface of the second gate structure.
8 . The semiconductor device of claim 1 , further comprising a bottom source/drain contact in contact with one of the first source/drain epitaxy structures, wherein the bottom source/drain contact has an L-shape cross-sectional profile.
9 . A semiconductor device, comprising:
a first transistor over a substrate, comprising:
a first semiconductor channel layer;
a first gate structure wrapping around the first semiconductor channel layer; and
first source/drain epitaxy structures on opposite ends of the first semiconductor channel layer;
a second transistor vertically above the first transistor, comprising:
a second semiconductor channel layer;
a second gate structure wrapping around the second semiconductor channel layer; and
second source/drain epitaxy structures on opposite ends of the second semiconductor channel layer; and
a bottom gate contact in contact with the first gate structure and spaced apart from the second gate structure, wherein a top surface of the bottom gate contact is higher than a top surface of the first semiconductor channel layer, and a bottom surface of the bottom gate contact is lower than a bottom surface of the first semiconductor channel layer.
10 . The semiconductor device of claim 9 , further comprising a shallow trench isolation structure over the substrate, wherein the first gate structure comprise a gate electrode, and the gate electrode has a portion vertically between the bottom gate contact and the shallow trench isolation structure.
11 . The semiconductor device of claim 10 , wherein the portion of the gate electrode is in contact with the bottom surface of the bottom gate contact.
12 . The semiconductor device of claim 9 , further comprising an isolation structure between the bottom gate contact and the second gate structure, wherein the isolation structure has a first portion vertically between the first gate structure and the second gate structure.
13 . The semiconductor device of claim 12 , wherein the isolation structure has a second portion vertically between the first gate structure and the substrate.
14 . The semiconductor device of claim 12 , wherein the isolation structure wraps around the first semiconductor channel layer in a cross-sectional view.
15 . The semiconductor device of claim 12 , wherein the first gate structure comprises a gate electrode, and the gate electrode has a portion extending from a bottom surface of the isolation structure to the bottom surface of the bottom gate contact.
16 . A method, comprising:
forming a first semiconductor layer and a second semiconductor layer over a substrate;
forming a first gate dielectric layer having a first portion wrapping around the first semiconductor layer and a second portion wrapping around the second semiconductor layer;
forming a first gate electrode having a first portion wrapping around the first semiconductor layer and a second portion wrapping around the second semiconductor layer;
forming an isolation structure wrapping around the first semiconductor layer and the second semiconductor layer;
etching back a portion of the isolation structure to expose the second portion of the first gate electrode;
removing the second portion of the first gate electrode;
forming a second gate dielectric layer wrapping around the second semiconductor layer; and
forming a second gate electrode wrapping around the second semiconductor layer.
17 . The method of claim 16 , wherein etching back the isolation structure is performed such that the first portion of the first gate electrode remains covered by the etched portion of the isolation structure.
18 . The method of claim 16 , wherein the second gate dielectric layer is in contact with the second portion of the first gate dielectric layer.
19 . The method of claim 16 , further comprising forming a bottom gate contact in the isolation structure, wherein the bottom gate contact is in contact with a third portion of the first gate electrode extending over a shallow trench isolation structure over the substrate.
20 . The method of claim 16 , further comprising:
forming sacrificial layers alternating with the first semiconductor layer and the second semiconductor layer; and
removing the sacrificial layers prior to forming the first gate dielectric layer.