Method for forming source/drain contacts
A semiconductor device includes a first transistor in a first region of a first conductivity type and a second transistor in a second region of a second conductivity type opposite to the first conductivity type. The first transistor includes a first gate stack, a first epitaxial feature in a source/drain (S/D) region of the first region, and a first metal silicide layer over the first epitaxial feature. The second transistor includes a second gate stack, a second epitaxial feature in an S/D region of the second region, a dopant-containing implant layer over the second epitaxial feature, and a second metal silicide layer over the dopant-containing implant layer. The dopant-containing implant layer includes a metallic dopant. A lowest point of a top surface of the first epitaxial feature is below a lowest point of a top surface of the second epitaxial feature.
1 . A semiconductor device, comprising:
a first transistor in a first region of a first conductivity type including:
a first gate stack;
a first gate spacer over sidewalls of the first gate stack;
a first epitaxial feature in a source/drain (S/D) region of the first region; and
a first metal silicide layer over the first epitaxial feature; and
a second transistor in a second region of a second conductivity type opposite to the first conductivity type including:
a second gate stack;
a second gate spacer over sidewalls of the second gate stack;
a second epitaxial feature in an S/D region of the second region;
a dopant-containing implant layer over the second epitaxial feature, wherein the dopant-containing implant layer includes a metallic dopant, wherein the second epitaxial feature is free of the metallic dopant; and
a second metal silicide layer over the dopant-containing implant layer,
wherein a lowest point of a top surface of the first epitaxial feature is below a lowest point of a top surface of the second epitaxial feature,
wherein the top surface of the first epitaxial feature and the top surface of the second epitaxial feature each have a concave profile.
2 . The semiconductor device of claim 1 , wherein the first conductivity type is an n-type, and the second conductivity type is a p-type.
3 . The semiconductor device of claim 1 , wherein the metallic dopant is gallium.
4 . The semiconductor device of claim 3 , wherein the dopant-containing implant layer further includes boron.
5 . The semiconductor device of claim 1 , wherein the first and second metal silicide layers include different metallic elements.
6 . The semiconductor device of claim 5 , wherein the second metal silicide layer includes the metallic dopant and the first metal silicide layer is substantially free of the metallic dopant.
7 . The semiconductor device of claim 1 , wherein a first vertical distance between a bottom surface of the first gate spacer and the lowest point of the top surface of the first epitaxial feature is greater than a second vertical distance between a bottom surface of the second gate spacer and the lowest point of the top surface of the second epitaxial feature.
8 . The semiconductor device of claim 1 , wherein the first epitaxial feature is substantially free of the metallic dopant.
9 . The semiconductor device of claim 1 , wherein the second epitaxial feature and the dopant-containing implant layer both include silicon and germanium.
10 . A semiconductor device, comprising:
a first source/drain (S/D) region, a second S/D region, and a channel region connecting the first and second S/D regions;
a gate structure over the channel region;
a first S/D feature comprising silicon germanium disposed in the first S/D region, wherein a top portion of the first S/D feature is doped with gallium and a bottom portion of the first S/D feature is free of gallium;
a second S/D feature disposed in the second S/D region, wherein the second S/D feature is free of gallium;
a metal silicide layer over a top surface of the first S/D feature; and
an S/D contact disposed on the metal silicide layer and electrically coupled to the first S/D feature.
11 . The semiconductor device of claim 10 , wherein the metal silicide layer includes gallium.
12 . The semiconductor device of claim 10 , wherein the top surface of the first S/D feature is below a top surface of the second S/D feature.
13 . The semiconductor device of claim 12 , wherein the top surface of the first S/D feature has a concave profile, and the top surface of the second S/D feature is substantially flat.
14 . The semiconductor device of claim 10 , wherein the top portion of the first S/D feature is also doped with boron.
15 . The semiconductor device of claim 10 , wherein the second S/D feature includes silicon germanium.
16 . The semiconductor device of claim 10 , further comprising:
a gate spacer layer disposed on sidewalls of the gate structure;
a contact etch stop layer (CESL) disposed on sidewalls of the gate spacer layer; and
a protective dielectric layer interposing the CESL and the S/D contact.
17 . A semiconductor device comprising:
an n-type transistor region including:
a first gate stack;
a first gate spacer over sidewalls of the first gate stack;
an n-type epitaxial feature in a source/drain (S/D) region of the n-type transistor region; and
a first metal silicide layer over the n-type epitaxial feature; and
a p-type transistor region including:
a second gate stack;
a second gate spacer over sidewalls of the second gate stack;
a silicon germanium containing epitaxial feature in an S/D region of the p-type transistor region, wherein a top portion of the silicon germanium containing epitaxial feature also contains gallium, wherein a bottom portion of the silicon germanium containing epitaxial feature is free of gallium, and wherein a thickness of the bottom portion of the silicon germanium containing epitaxial feature is greater than a thickness of the top portion of the silicon germanium containing epitaxial feature; and
a second metal silicide layer over the top portion of the silicon germanium containing epitaxial feature.
18 . The semiconductor device of claim 17 , wherein the silicon germanium containing epitaxial feature further contains boron.
19 . The semiconductor device of claim 17 , wherein a first vertical distance between a bottom surface of the first gate spacer and a lowest point of an upper surface of the n-type epitaxial feature is greater than a second vertical distance between a bottom surface of the second gate spacer and a lowest point of an upper surface of the silicon germanium containing epitaxial feature.
20 . The semiconductor device of claim 17 , wherein a lowest point of a top surface of the n-type epitaxial feature is below a lowest point of a top surface of the silicon germanium containing epitaxial feature.