IP Library › Granted Patent US 12672347
Granted Patent B2
US 12672347 · App. 17/847,628 · Granted Jun 30, 2026

Lower device access in stacked transistor devices

Inventors: Cheng-Ying Huang (Hillsboro, OR); Patrick Morrow (Portland, OR); Quan Shi (Portland, OR); Rohit Galatage (Hillsboro, OR); Nicole K. Thomas (Portland, OR); Munzarin F. Qayyum (Hillsboro, OR); Jami A. Wiedemer (Scappoose, OR); Gilbert Dewey (Beaverton, OR); Mauro J. Kobrinsky (Portland, OR); Marko Radosavljevic (Portland, OR); Jack T. Kavalieros (Portland, OR)
Assignee: INTEL CORPORATION
H10D84/853H10D30/6735H10D30/6757H10D62/121H10D62/151H10W20/20
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Quick Facts
Patent No.
US 12672347
App. No.
17/847,628
Granted
Jun 30, 2026
Kind
B2
Abstract

An integrated circuit structure includes a device layer including an upper device above a lower device. The upper device includes an upper source or drain region, and an upper source or drain contact coupled to the upper source or drain region. The lower device includes a lower source or drain region. A first conductive feature is below the device layer, where the first conductive feature is coupled to the lower source or drain region. A second conductive feature vertically extends through the device layer. In an example, the second conductive feature is to couple (i) the first conductive feature below the device layer and (ii) an interconnect structure above the device layer. Thus, the first and second conductive features facilitate a connection between the interconnect structure on the frontside of the integrated circuit and the lower source or drain region towards the backside of the integrated circuit.

Claims (43)

1 . An integrated circuit, comprising:

a device layer including an upper device stacked above a lower device, wherein the upper device comprises (i) an upper source or drain region and (ii) an upper source or drain contact coupled to the upper source or drain region, and wherein the lower device comprises a lower source or drain region;

a first conductive feature below the device layer, the first conductive feature coupled to the lower source or drain region; and

a second conductive feature vertically extending through the device layer, the second conductive feature to couple (i) the first conductive feature below the device layer and (ii) an interconnect structure above the device layer,

wherein the first conductive feature extends laterally from under the second conductive feature to under the lower source or drain region, and wherein the first conductive feature has (i) a first thickness under the second conductive feature and (ii) a second thickness under the lower source or drain region, the first thickness being within 1 nm of the second thickness.

2 . The integrated circuit of claim 1 , wherein the first conductive feature is directly coupled to the lower source or drain region, and the second conductive feature lands on the first conductive feature.

3 . The integrated circuit of claim 1 , wherein the upper source or drain contact extends within the upper source or drain region.

4 . The integrated circuit of claim 1 , wherein the first conductive feature does not extend within the lower source or drain region.

5 . The integrated circuit of claim 1 , wherein the first conductive feature is a backside contact and the second conductive feature is a via extending through the device layer.

6 . The integrated circuit of claim 1 , wherein the second conductive feature has a top surface that is coplanar with or above a top surface of the upper source or drain contact.

7 . The integrated circuit of claim 1 , wherein a top surface of the second conductive feature is within a horizontal plane that is at most at a vertical distance of 3 nm from another horizontal plane in which resides a top surface of the upper source or drain contact.

8 . The integrated circuit of claim 1 , wherein a top surface of the second conductive feature is within a horizontal plane that is at least at a vertical distance of 5 nm from another horizontal plane in which resides a top surface of the upper source or drain contact.

9 . The integrated circuit of claim 1 , wherein a top surface of the second conductive feature is in contact with a third conductive feature of a metallization layer above the device layer.

10 . The integrated circuit of claim 1 , wherein the first conductive feature is directly coupled to the lower source or drain region, and the integrated circuit further comprises an additional interconnect structure comprising a plurality of interconnect features, the additional interconnect structure below the device layer, the additional interconnect structure to directly couple the first conductive feature with the second conductive feature.

11 . The integrated circuit of claim 1 , wherein:

the upper source or drain region is a first upper source or drain region, the upper source or drain contact is a first upper source or drain contact, the lower source or drain region is a first lower source or drain region;

the upper device further comprises (i) a second upper source or drain region and (ii) a second upper source or drain contact coupled to the second upper source or drain region;

the lower device comprises a second lower source or drain region; and

the second upper source or drain contact extends through the second upper source or drain region, and is electrically coupled to the second lower source or drain region through a conductive layer, the conductive layer within an isolation region between the second upper source or drain region and the second lower source or drain region.

12 . The integrated circuit of claim 1 , wherein the upper source or drain region is above the lower source or drain region, and the integrated circuit further comprises an isolation region comprising nonconductive material between the upper source or drain region and the lower source or drain region.

13 . An integrated circuit structure, comprising:

a lower device;

an upper device above the lower device, wherein the lower device comprises a lower source or drain region;

a lower source or drain contact below, and coupled to, the lower source or drain region; and

a conductive via to couple the lower source or drain contact to an interconnect structure above the upper device,

wherein the lower source or drain contact extends laterally from under the conductive via to under the lower source or drain region, and wherein the lower source or drain contact has (i) a first thickness under the conductive via and (ii) a second thickness under the lower source or drain region, wherein a difference between the first thickness and the second thickness is at least 1 nm.

14 . The integrated circuit structure of claim 13 , wherein the lower source or drain contact is directly coupled to the lower source or drain region, and wherein the conductive via lands on a surface of the lower source or drain contact and extends upward to contact the interconnect structure above the upper device.

15 . The integrated circuit structure of claim 13 , wherein the lower source or drain contact is directly coupled to the lower source or drain region, and wherein the conductive via is coupled to the lower source or drain contact through an additional interconnect structure that is below the lower device, the additional interconnect structure including one or more conductive interconnect features.

16 . The integrated circuit structure of claim 13 , wherein the upper device comprises an upper source or drain region, and wherein the integrated circuit further comprises:

an upper source or drain contact at least in part above, and coupled to, the upper source or drain region, wherein the upper source or drain contact couples the upper source or drain region to the interconnect structure above the upper device.

17 . An integrated circuit structure, comprising:

a lower device;

an upper device above the lower device, wherein the lower device comprises a lower source or drain region;

an interconnect structure above the upper device; and

a plurality of conductive features to couple the lower source or drain region to the interconnect structure above the upper device, wherein the plurality of conductive features comprises a first conductive feature coupled to a bottom surface of the lower source or drain region and a second conductive feature extending from the first conductive feature to the interconnect structure above the upper device,

wherein the first conductive feature extends laterally from under the second conductive feature to under the lower source or drain region, and wherein the first conductive feature has (i) a first thickness under the second conductive feature and (ii) a second thickness under the lower source or drain region, the first thickness being within 1 nm of the second thickness.

18 . The integrated circuit structure of claim 17 , wherein:

the lower source or drain region is a first lower source or drain region; and

the lower device further comprises (i) a second lower source or drain region, and (ii) a body comprising semiconductor material laterally extending from the first lower source or drain region to the second lower source or drain region.

19 . The integrated circuit structure of claim 18 , wherein the body comprises a fin, a nanoribbon, a nanowire, or a nanosheet.

20 . The integrated circuit structure of claim 17 , wherein the second conductive feature extends upward to contact an interconnect feature of the interconnect structure above the upper device.

21 . The integrated circuit structure of claim 17 , wherein the first conductive feature is directly coupled to the bottom surface of the lower source or drain region and to the second conductive feature.

22 . The integrated circuit structure of claim 17 , wherein the first conductive feature is directly coupled to the bottom surface of the lower source or drain region, and the integrated circuit further comprises one or more additional interconnect features below the lower device, the one or more additional interconnect features to directly couple the first conductive feature with the second conductive feature.