IP Library › Granted Patent US 12672355
Granted Patent B2
US 12672355 · App. 17/458,112 · Granted Jun 30, 2026

Gallium nitride (GaN) epitaxy on patterned substrate for integrated circuit technology

Inventors: Pratik Koirala (Portland, OR); Paul Nordeen (Hillsboro, OR); Tushar Talukdar (Wilsonville, OR); Kimin Jun (Portland, OR); Thomas Hoff (Hillsboro, OR); Han Wui Then (Portland, OR); Nicole K. Thomas (Portland, OR); Marko Radosavljevic (Portland, OR); Paul B. Fischer (Portland, OR)
Assignee: Intel Corporation
H10D88/101H10D1/68H10D30/475H10D62/405H10D62/80H10D84/01H10D84/038H10D84/08H10D88/01H10W20/20
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Quick Facts
Patent No.
US 12672355
App. No.
17/458,112
Granted
Jun 30, 2026
Kind
B2
Abstract

Gallium nitride (GaN) epitaxy on patterned substrates for integrated circuit technology is described. In an example, an integrated circuit structure includes a material layer including gallium and nitrogen, the material layer having a first side and a second side opposite the first side. A plurality of fins is on the first side of the material layer, the plurality of fins including silicon. A device layer is on the second side of the material layer, the device layer including one or more GaN-based devices.

Claims (42)

1 . An integrated circuit structure, comprising:

a material layer comprising gallium and nitrogen, the material layer having a first side and a second side opposite the first side;

a plurality of semiconductor fins on the first side of the material layer, each of the plurality of semiconductor fins in direct contact with and entirely above the first side of the material layer, the plurality of semiconductor fins comprising silicon, wherein individual ones of the plurality of semiconductor fins are discontinuous with one another; and

a device layer on the second side of the material layer, the device layer comprising one or more GaN-based devices.

2 . The integrated circuit structure of claim 1 , wherein the plurality of semiconductor fins is coupled to the material layer at a Si(111) crystal plane.

3 . The integrated circuit structure of claim 1 , wherein the plurality of semiconductor fins has a spacing of approximately 100 nanometers between neighboring semiconductor fins.

4 . The integrated circuit structure of claim 1 , wherein the device layer is bonded to a second device layer comprising silicon, the second device layer comprising one or more Si-based devices.

5 . The integrated circuit structure of claim 1 , wherein a component is included in a spacing between a pair of the plurality of semiconductor fins, the component selected from the group consisting of a through silicon via, a metal-insulator-metal capacitor, and a resonator.

6 . A computing device, comprising:

a board; and

a component coupled to the board, the component including an integrated circuit structure, comprising:

a material layer comprising gallium and nitrogen, the material layer having a first side and a second side opposite the first side;

a plurality of semiconductor fins on the first side of the material layer, the plurality of semiconductor fins comprising silicon, each of the plurality of semiconductor fins in direct contact with and entirely above the first side of the material layer, wherein individual ones of the plurality of semiconductor fins are discontinuous with one another; and

a device layer on the second side of the material layer, the device layer comprising one or more GaN-based devices.

7 . The computing device of claim 6 , further comprising:

a memory coupled to the board.

8 . The computing device of claim 6 , further comprising:

a communication chip coupled to the board.

9 . The computing device of claim 6 , further comprising:

a camera coupled to the board.

10 . The computing device of claim 6 , wherein the component is a packaged integrated circuit die.

11 . The computing device of claim 6 , wherein the plurality of semiconductor fins is coupled to the material layer at a Si(111) crystal plane.

12 . The computing device of claim 6 , wherein the plurality of semiconductor fins has a spacing of approximately 100 nanometers between neighboring semiconductor fins.

13 . The computing device of claim 6 , wherein the device layer is bonded to a second device layer comprising silicon, the second device layer comprising one or more Si-based devices.

14 . The computing device of claim 6 , wherein a component is included in a spacing between a pair of the plurality of semiconductor fins, the component selected from the group consisting of a through silicon via, a metal-insulator-metal capacitor, and a resonator.

15 . A method of fabricating an integrated circuit structure, the method comprising:

forming a material layer comprising gallium and nitrogen, the material layer having a first side and a second side opposite the first side;

forming a plurality of semiconductor fins on the first side of the material layer, the plurality of semiconductor fins comprising silicon, each of the plurality of semiconductor fins in direct contact with and entirely above the first side of the material layer, wherein individual ones of the plurality of semiconductor fins are discontinuous with one another; and

forming a device layer on the second side of the material layer, the device layer comprising one or more GaN-based devices.

16 . The method of claim 15 , wherein the plurality of semiconductor fins is coupled to the material layer at a Si(111) crystal plane.

17 . The method of claim 15 , wherein the plurality of semiconductor fins has a spacing of approximately 100 nanometers between neighboring semiconductor fins.

18 . The method of claim 15 , wherein the device layer is bonded to a second device layer comprising silicon, the second device layer comprising one or more Si-based devices.

19 . The method of claim 15 , wherein a component is included in a spacing between a pair of the plurality of semiconductor fins, the component selected from the group consisting of a through silicon via, a metal-insulator-metal capacitor, and a resonator.

20 . The method of claim 15 , wherein forming the plurality of semiconductor fins comprises forming the material layer on a substrate having trenches therein, and then removing a portion of the substrate to reveal the trenches.

21 . An integrated circuit structure, comprising:

a material layer comprising gallium and nitrogen, the material layer having a first side and a second side opposite the first side;

a plurality of semiconductor fins on the first side of the material layer, the plurality of semiconductor fins comprising silicon, wherein individual ones of the plurality of semiconductor fins are discontinuous with one another; and

a device layer on the second side of the material layer, the device layer comprising one or more GaN-based devices, wherein the device layer is bonded to a second device layer comprising silicon, the second device layer comprising one or more Si-based devices.

22 . An integrated circuit structure, comprising:

a material layer comprising gallium and nitrogen, the material layer having a first side and a second side opposite the first side;

a plurality of semiconductor fins on the first side of the material layer, the plurality of semiconductor fins comprising silicon, wherein individual ones of the plurality of semiconductor fins are discontinuous with one another; and

a device layer on the second side of the material layer, the device layer comprising one or more GaN-based devices, wherein a component is included in a spacing between a pair of the plurality of semiconductor fins, the component selected from the group consisting of a through silicon via, a metal-insulator-metal capacitor, and a resonator.