SPAD pixel circuits and methods thereof for direct time of flight sensors
The present invention relates generally to sensing devices. In a specific embodiment, the present invention provides a SPAD pixel device that include a p-type material that partially encloses an n-type material. The junction between the p-type material and the n-type material is three dimensional and includes both a horizontal area and lateral areas. The SPAD pixel device also includes isolation structures that separate the SPAD pixel device from others. There are other embodiments as well.
1 . A backside illuminated (BSI) single-photon avalanche diode (SPAD) sensor device comprising:
a silicon material having a front side and a back side; a first deep trench structure positioned within the silicon material;
a second deep trench structure positioned within the silicon material;
an aperture positioned on the back side and between the first deep trench structure and the second deep trench structure;
an n-type material having a first top region and a first bottom region, the first bottom region bordering the back side, the first top region comprising a top surface and a first sidewall and a second sidewall, the first sidewall and the second sidewall being positioned laterally relative to the top surface, the n-type material being characterized by a first width;
an n-type contact directly coupled to the n-type material and positioned within the first bottom region;
a p-type material having a second top region and a second bottom region, the second bottom region enclosing the first top surface and the first sidewall and the second sidewall, a top surface of the p-type material and a first sidewall of the p-type material being continuous, the p-type material being characterized by a second width, the second width being greater than the first width, a top surface of the p-type material directly interfacing the silicon material, a side surface of the p-type material directly interfacing the silicon material; and
a junction region configured at an interface between the first top region and the second bottom region, the junction region comprises an avalanche area for collecting photon-generated carriers, the junction region comprising an overlap region positioned between the first sidewall of the n-type material and the first sidewall of the p-type material;
wherein the p-type material is characterized by a concentration gradient that a concentration of p-type material decreases from a horizontal interface and lateral sidewall interfaces of the junction region toward the backside, the concentration gradient comprising a retrograde profile and being associated by a post-implantation anneal process, the concentration gradient being associated with multiple energies in implantation, the p-type material comprising a boron material having a concentration density of 1 E15 atoms/cm3 to 1 E18 atoms/cm3, the retrograde profiles creating a higher electric field to shorten a carrier travel time from the silicon material to the avalanche area and reduce jitter, the retrograde profile being offset from the front side to position the avalanche area away from the front side to prevent carriers generated by front-surface defects from reaching the avalanche area.
2 . The device of claim 1 further comprising a first shallow trench structure interfacing the first deep trench structure and a second shallow trench structure interfacing the second deep trench structure.
3 . The device of claim 2 further comprising a first p-type contact interfacing
the first shallow trench structure and a second p-type contact interfacing the second shallow trench structure.
4 . The device of claim 2 further comprising:
a first p-type contact configured within a vicinity of the first shallow trench structure and the front side; and
a second p-type contact configured within a vicinity of the second shallow trench structure and the front side.
5 . The device of claim 1 further comprising a P+ region positioned within a vicinity of the front side.
6 . The device of claim 1 further comprising a plurality of light trapping structures configured within a vicinity of the back side.
7 . The device of claim 1 further comprising a plurality of light trapping structures configured within a vicinity of the front side.
8 . The device of claim 1 wherein the junction region comprises an avalanche region.
9 . The device of claim 1 further comprising a first P-well structure partially enclosing the first deep trench structure and a second P-well structure partially enclosing the second deep trench structure.
10 . The device of claim 1 wherein the silicon material comprises an epitaxially grown silicon material.
11 . The device of claim 1 further comprising a passivate layer overlaying the aperture.
12 . The device of claim 1 wherein the p-type material is characterized by a graduated doping profile.
13 . The device of claim 1 further comprising an N-well region partially overlaying the first bottom region of the n-type material.
14 . A single-photon avalanche diode (SPAD) sensor device comprising:
a silicon material having a front side and a back side;
a first isolation structure positioned within the silicon material and bordering the back side;
a second isolation structure positioned within the silicon material and bordering the back side;
an n-type material having a first top region and a first bottom region, the first bottom region bordering the back side, the first top region comprising a top surface and a first sidewall and a second sidewall, the first sidewall and the second sidewall being positioned laterally relative to the top surface, the n-type material being characterized by a first width;
an n-type contact directly coupled to the n-type material and positioned within the first bottom region;
a p-type material having a second top region and a second bottom region, the p-type material being characterized by a radial concentration profile having a greatest doping concentration at a center of the p-type material, the second bottom region enclosing the first top surface and the first sidewall and the second sidewall, a top surface of the p-type material and a first sidewall of the p-type material being continuous, the p-type material being characterized by a second width, the second width being greater than the first width, a top surface of the p-type material directly interfacing the silicon material, a side surface of the p-type material directly interfacing the silicon material; and
a junction region configured at an interface between the first top region and the second bottom region, the junction region comprising an overlap region positioned between the first sidewall of the n-type material and the first sidewall of the p-type material;
wherein the p-type material is characterized by a concentration gradient that a concentration of p-type material decreases from a horizontal interface and lateral sidewall interfaces of the junction region toward the backside, the concentration gradient comprising a retrograde profile and being associated by a post-implantation anneal process, the concentration gradient being associated with multiple energies in implantation, the p-type material comprising a boron material having a concentration density of 1 E15 atoms/cm3 to 1 E18 atoms/cm3, the retrograde profiles creating a higher electric field to shorten a carrier travel time from the silicon material to the avalanche area and reduce jitter, the retrograde profile being offset from the front side to position the avalanche area away from the front side to prevent carriers generated by front-surface defects from reaching the avalanche area.
15 . The device of claim 14 further comprising an aperture positioned on the back side and between the first isolation structure and the second isolation structure.
16 . The device of claim 15 further comprising a passivation layer overlaying the aperture and the first isolation structure.
17 . The device of claim 14 wherein:
the first isolation structure comprises a first deep trench structure and a first p-well structure, the first p-well structure partially enclosing the first deep trench structure; and
the second isolation structure comprises a second deep trench structure and a second p-well structure, the second p-well structure partially enclosing the second deep trench structure.
18 . The device of claim 17 further comprising a first shallow trench structure interfacing the first p-well structure and a second shallow trench structure interfacing the second p-well structure.
19 . A frontside illuminated (FSI) single-photon avalanche diode (SPAD) sensor device comprising:
a silicon material having a front side and a back side;
a first isolation structure positioned within the silicon material;
a second isolation structure positioned within the silicon material;
an aperture positioned on the front side and configured between the first isolation structure and the second isolation structure;
an n-type material having a first top region and a first bottom region, the first top region bordering the back side, the first bottom region comprising a bottom surface and a first sidewall and a second sidewall, the first sidewall and the second sidewall being positioned laterally relative to the bottom surface, the n-type material being characterized by a first width;
an n-type contact directly coupled to the n-type material and positioned within the first top region;
a p-type material having a second top region and a second bottom region, the second top region completely enclosing the first bottom surface and partially enclosing the first sidewall and the second sidewall, the bottom surface and the first sidewall of the p-type material being continuous, the p-type material being characterized by a second width, the second width being greater than the first width, the second top region is characterized by a first doping concentration, the second bottom region is characterized by a second doping concentration, the first doping concentration being lower than the second doping concentration; and
an active junction region configured at an interface between the first bottom region and the second top region, the active junction region comprising an overlap region positioned between the first sidewall of the n-type material and the first sidewall of the p-type material;
wherein the p-type material is characterized by a concentration gradient that a concentration of p-type material decreases from near the junction region toward the backside, the concentration gradient comprising a retrograde profile and being associated by a post-implantation anneal process, the concentration gradient being associated with multiple energies in implantation, the p-type material comprising a boron material having a concentration density of 1E15 atoms/cm3 to 1E18 atoms/cm3, the retrograde profiles creating a higher electric field to shorten a carrier travel time from the silicon material to the avalanche area and reduce jitter, the retrograde profile being offset from the front side to position the avalanche area away from the front side to prevent carriers generated by front-surface defects from reaching the avalanche area.
20 . The device of claim 19 wherein the first isolation structure comprises a p-well region.