IP Library Granted Patent US 12672433
Granted Patent B2
US 12672433 · App. 17/735,489 · Granted Jun 30, 2026

Display device

Inventors: Sang Duk Lee (Yongin-si, KR); Hyun A Lee (Seoul, KR); Mi Sun Kim (Hwaseong-si, KR); Sun Ok Oh (Hwaseong-si, KR); Ki Kyung Youk (Bucheon-si, KR)
Assignee: SAMSUNG DISPLAY CO., LTD.
H10K59/122H10W72/221H10W72/232H10W72/248H10W72/252H10W72/29H10W72/321H10W72/90H10W72/9445H10W74/15H10W90/722H10W90/732H10W99/00
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Quick Facts
Patent No.
US 12672433
App. No.
17/735,489
Granted
Jun 30, 2026
Kind
B2
Abstract

A display device comprises a display panel including a display area including pixels, and a pad area adjacent to the display area, and a driving integrated circuit mounted on the pad area, wherein the pad area includes a stud pad area located at an edge of the pad area and including at least one stud pad electrode, the driving integrated circuit includes a circuit base, and at least one stud bump area overlapping the stud pad area in a thickness direction of the display device and including at least one stud bump, and the at least one stud pad electrode overlaps an edge portion of the at least one stud bump.

Claims (78)

1 . A display device comprising:

a display panel including:

a display area including pixels; and

a pad area adjacent to the display area; and

a driving integrated circuit mounted on the pad area, wherein

the pad area includes a stud pad area located at an edge of the pad area and including at least one stud pad electrode,

the driving integrated circuit includes:

a circuit base; and

at least one stud bump area overlapping the stud pad area in a thickness direction of the display device and including at least one stud bump,

the at least one stud pad electrode overlaps an edge portion of the at least one stud bump in plan view and the stud bump extends through an entire thickness of the stud pad electrode at a center thereof, wherein

the at least one stud pad electrode includes stud pad patterns separated from each other with a separation space between the stud pad patterns in a plan view.

2 . The display device of claim 1 , wherein the pad area further includes:

an output pad area adjacent to the display area and including output pad electrodes; and

an input pad area located below the output pad area in a plan view and including input pad electrodes.

3 . The display device of claim 1 , wherein the stud pad patterns do not overlap a center portion of the at least one stud bump in the thickness direction.

4 . The display device of claim 1 , wherein at least one stud pad pattern includes a portion that does not overlap the at least one stud bump in the thickness direction.

5 . A display device comprising:

a display panel including:

a display area including pixels; and

a pad area adjacent to the display area; and

a driving integrated circuit mounted on the pad area, wherein

the pad area includes a stud pad area located at an edge of the pad area and including at least one stud pad electrode,

the driving integrated circuit includes:

a circuit base; and

at least one stud bump area overlapping the stud pad area in a thickness direction of the display device and including at least one stud bump,

the at least one stud pad electrode overlaps an edge portion of the at least one stud bump in plan view, wherein

the at least one stud pad electrode includes stud pad patterns separated from each other with a separation space between the stud pad patterns in a plan view, and

the stud pad patterns overlap the edge portion of the at least one stud bump in the thickness direction and include portions that protrude outward from the edge portion of the at least one stud bump in the plan view, and

wherein the stud pad patterns are disposed in a closed loop shape in a plan view.

6 . The display device of claim 5 , wherein the stud pad patterns are symmetrical with respect to a direction in a plan view.

7 . The display device of claim 6 , wherein the display panel further includes:

a base substrate; and

at least one inorganic layer on the base substrate, the at least one inorganic layer includes a stud hole penetrating in the thickness direction between the stud pad patterns symmetrical with respect to the direction, wherein a side surface of the at least one inorganic layer is exposed through the stud hole.

8 . The display device of claim 7 , wherein

the at least one stud bump fills and is disposed in the stud hole, and

the at least one stud bump directly contacts at least one of the stud pad patterns.

9 . The display device of claim 8 , wherein the at least one stud bump directly contacts a top surface and a side surface of the at least one of the stud pad patterns, and

the at least one stud bump directly contacts the side surface of the at least one inorganic layer exposed through the stud hole.

10 . The display device of claim 8 , wherein the at least one stud bump is ultrasonically bonded to the at least one of the stud pad patterns.

11 . The display device of claim 2 , wherein at least one of the input pad electrodes, at least one of the output pad electrodes, and at least one of the stud pad patterns are located on a same layer.

12 . The display device of claim 2 , wherein

the driving integrated circuit includes:

an output bump area overlapping the output pad area in the thickness direction and including output bumps; and

an input bump area overlapping the input pad area in the thickness direction and including input bumps, and

the at least one stud bump area is located outside the output bump area and the input bump area in a plan view.

13 . The display device of claim 12 , wherein

a shape of the driving integrated circuit in a plan view is a rectangular shape including long sides extending in a first direction and short sides extending in a second direction intersecting the first direction, and

the at least one stud bump area is located between the output bump area and a short side of the driving integrated circuit in a plan view.

14 . The display device of claim 13 , wherein

the at least one stud bump area includes stud bump areas,

a shape of the driving integrated circuit in a plan view has four corners formed by the long sides and the short sides, and

the stud bump areas are located adjacent to the four corners.

15 . The display device of claim 13 , wherein

a shape of the driving integrated circuit in a plan view includes edges located between one of the long sides and one of the short sides adjacent to each other and extending in a direction different from the one of the long sides and the one of the short sides,

the at least one stud bump area includes stud bump areas, and

the stud bump areas are located adjacent to the edges.

16 . The display device of claim 15 , wherein each one of the edges has a round shape.

17 . The display device of claim 12 , wherein

at least one of the input bumps and at least one of the input pad electrodes directly contact each other, and

a non-conductive adhesive member is disposed between the at least one of the input bumps and another one of the input bumps adjacent thereto and between the at least one of the input pad electrodes and another of the input pad electrodes adjacent thereto.

18 . A display device comprising:

a display area including pixels;

a first pad area adjacent to the display area; and

a second pad area farther from the display area than the first pad area in a plan view, wherein:

the first pad area includes:

an output pad area adjacent to the display area and including output pad electrodes;

an input pad area located below the output pad area in a plan view and including input pad electrodes; and

a stud pad area located at an edge of the first pad area and including one or more stud pad electrodes, and

the one or more stud pad electrodes include stud pad patterns separated from each other with a separation space between the one or more stud pad electrodes in a plan view,

the stud pad patterns are arranged in a closed loop shape in a plan view,

the output pad area includes at least one resistance measurement pad,

the second pad area includes at least one resistance test point pad, and

the resistance measurement pad and the resistance test point pad are electrically connected through a resistance measurement line.

19 . The display device of claim 18 , wherein

the at least one resistance measurement pad is disposed between the output pad electrodes in a plan view, and

the at least one resistance test point pad is disposed between the input pad electrodes in a plan view.

20 . The display device of claim 18 , wherein the stud pad patterns have a symmetrical shape with respect to a direction in a plan view.

21 . The display device of claim 1 , wherein the stud pad patterns include portions that protrude outward from the edge portion of the at least one stud bump in the plan view.