Driving backplane and method for manufacturing the same, display panel, and display apparatus

1 . A driving backplane, comprising:

a substrate;

a first conductive layer disposed on the substrate, wherein the first conductive layer includes a first electrode, the first electrode includes a first sub-electrode and a second sub-electrode surrounding the first sub-electrode, and the second sub-electrode and the first sub-electrode have no gap therebetween;

an insulating layer disposed on a side of the first conductive layer away from the substrate; and

a second conductive layer disposed on a side of the insulating layer away from the substrate, wherein

the second conductive layer includes a second electrode; an orthographic projection of the second electrode on the substrate coincides with an orthographic projection of the first sub-electrode on the substrate; and the first sub-electrode, the second electrode and a portion of the insulating layer located therebetween constitute a first capacitor; and

the second conductive layer further includes third electrodes located on two opposite sides of the second electrode; the third electrodes are connected to the second electrode, orthographic projections of the third electrodes on the substrate are within an orthographic projection of the second sub-electrode on the substrate, and an edge of a third electrode of the third electrodes away from the second electrode is flush with a portion of an edge of the second sub-electrode; and the third electrode, a portion of the second sub-electrode that overlaps with the third electrode and a portion of the insulating layer located therebetween constitute a second capacitor.

2 . The driving backplane according to claim 1 , wherein the first capacitor is included in a pixel circuit in the driving backplane.

3 . The driving backplane according to claim 1 , wherein the second electrode has no opening.

4 . The driving backplane according to claim 1 , wherein a distance between an edge of the orthographic projection of the second electrode on the substrate and an edge of an orthographic projection of the first electrode on the substrate is greater than or equal to 1 μm.

5 . The driving backplane according to claim 1 , wherein

a width of the third electrode is less than a width of the second electrode.

6 . The driving backplane according to claim 5 , wherein widths of the third electrodes located on the two opposite sides of the second electrode are equal.

7 . The driving backplane according to claim 5 , wherein the number of second electrodes is multiple;

the second conductive layer further includes a connection line; an orthographic projection of the connection line on the substrate does not overlap with the orthographic projection of the second sub-electrode on the substrate; the connection line is connected to two adjacent third electrodes, and the two adjacent third electrodes are connected to two adjacent second electrodes of the second electrodes, respectively; and

a width of the connection line is equal to the width of the third electrode.

8 . The driving backplane according to claim 1 , further comprising:

a third conductive layer disposed on a side of the second conductive layer away from the substrate, wherein the third conductive layer includes a first conductive pattern; and

the first conductive pattern is coupled to the second sub-electrode.

9 . The driving backplane according to claim 8 , wherein an orthographic projection of the first conductive pattern on the substrate does not overlap with the orthographic projection of the second electrode on the substrate.

10 . The driving backplane according to claim 8 , further comprising:

an active pattern layer disposed on the substrate and located on a side of the substrate proximate to the first conductive layer, wherein the active pattern layer includes a semiconductor pattern and a conductor pattern; and

the first conductive pattern is further coupled to a portion of the conductor pattern of the active pattern layer.

11 . The driving backplane according to claim 10 , wherein a position where the first conductive pattern is coupled to the second sub-electrode is closer to a position where the first conductive pattern is coupled to the active pattern layer than a position of the first sub-electrode is.

12 . The driving backplane according to claim 8 , wherein the third conductive layer further includes power supply voltage lines; a power supply voltage line of the power supply voltage lines is coupled to the second electrode;

the second conductive layer further includes a second conductive pattern; and

the second conductive pattern is coupled to the power supply voltage line.

13 . The driving backplane according to claim 12 , wherein the third conductive layer further includes data lines;

an orthographic projection of the second conductive pattern on the substrate overlaps with an orthographic projection of a data line of the data lines on the substrate.

14 . The driving backplane according to claim 12 , wherein the number of second electrodes is multiple; the second conductive layer further includes a connection line, the connection line is connected to two adjacent third electrodes, and the two adjacent third electrodes are connected to two adjacent second electrodes of the second electrodes, respectively; and an extending direction of the connection line intersects an extending direction of the power supply voltage lines.

15 . A display panel, comprising the driving backplane according to claim 1 .

16 . A display apparatus, comprising the display panel according to claim 15 .

17 . A method for manufacturing a driving backplane, comprising:

forming a first conductive layer on a substrate, the first conductive layer including a first electrode;

forming an insulating layer on a side of the driving backplane away from the substrate; and

forming a second conductive layer on a side of the insulating layer away from the substrate, wherein

the second conductive layer includes a second electrode; the first electrode includes a first sub-electrode and a second sub-electrode; an orthographic projection of the first sub-electrode on the substrate coincides with an orthographic projection of the second electrode on the substrate; and the second sub-electrode surrounds the first sub-electrode; the first sub-electrode, the second electrode and a portion of the insulating layer located therebetween constitute a first capacitor; and

the second conductive layer further includes third electrodes located on two opposite sides of the second electrode; the third electrodes are connected to the second electrode, orthographic projections of the third electrodes on the substrate are within an orthographic projection of the second sub-electrode on the substrate, and an edge of a third electrode of the third electrodes away from the second electrode is flush with a portion of an edge of the second sub-electrode; and the third electrode, a portion of the second sub-electrode that overlaps with the third electrode and a portion of the insulating layer located therebetween constitute a second capacitor.

18 . The method according to claim 17 , wherein forming the second electrode, includes:

forming a conductive film on the side of the first conductive layer away from the substrate;

forming a photoresist layer on the conductive film;

exposing and developing the photoresist layer through a mask, so as to obtain a patterned photoresist layer, the patterned photoresist layer covering a portion of the conductive film located in a region where the first sub-electrode is located; and

removing the patterned photoresist layer and a portion of the conductive film that is located outside an orthographic projection of the patterned photoresist layer on the substrate through an etching process, so as to obtain the second electrode with no opening.