Image-based semiconductor device patterning method using deep neural network

1 . A semiconductor device patterning method, comprising:

generating an input image by imaging information about a pattern of a sample;

acquiring an output image of the pattern of the sample after a preset semiconductor process with respect to the sample;

generating a predictive model through learning using a Deep Neural Network (DNN) with the input image and the output image; and

predicting a pattern image after the semiconductor process for a pattern of a semiconductor device by using the predictive model,

wherein:

the information about the pattern of the sample is an After Develop Inspection (ADI) image for the pattern of the sample,

the output image is an After Cleaning Inspection (ACI) image for the pattern of the sample, and

the generating of the input image includes:

extracting a contour image from the ADI image; and

rasterizing the contour image.

2 . The method as claimed in claim 1 , wherein windowed bi-cubic filter is used in rasterizing the contour image.

3 . The method as claimed in claim 2 , further comprising:

interpolating a value of a level less than a pixel using a Shannon-sampling algorithm and a bi-linear or bi-cubic algorithm in the input image; and

extracting a critical dimension (CD) value from a threshold with a Newton-Raphson algorithm.

4 . The method as claimed in claim 1 , wherein:

the extracting of the contour image includes excluding the ADI image, when an average of pixel values of a n*n clip image (n is an integer greater than or equal to 2) is 255/j (j:2 to N, 8-bit image) among the N contour images, and a standard deviation of pixel values is less than a set value, and

the rasterizing of the contour image includes using an average value after rasterizing the N contour images.

5 . The method as claimed in claim 1 , further comprising generating a contour band from the contour image and excluding the contour image, when a value of the contour band is greater than a set value.

6 . The method as claimed in claim 1 , further comprising generating a density map for a full-chip of the sample, and adding the density map as the input image to a channel.

7 . The method as claimed in claim 1 , wherein the DNN includes a plurality of down-sample layers.

8 . A semiconductor device patterning method, comprising:

generating an input image by rasterizing a layout of a mask pattern corresponding to a pattern of a sample;

obtaining an image of an Optical Proximity Corrected (OPCed) layout for the mask pattern as an output image;

generating a predictive model through learning using a Deep Neural Network (DNN) with the input image and the output image;

predicting an image of an OPCed layout for a pattern of a semiconductor device by using the predictive model;

determining whether the predicted image of the OPCed layout satisfies a set condition;

manufacturing a mask based on the image of the OPCed layout when the condition is satisfied; and

forming a pattern on a semiconductor device by using the mask,

wherein the DNN includes a mask-layer that delimits or confines regions.

9 . The method as claimed in claim 8 , wherein the generating of the input image by rasterizing includes using a windowed bi-cubic filter in the rasterization, and

the method further comprises interpolating a value of a level less than a pixel using a Shannon-sampling algorithm and a bi-linear or bi-cubic algorithm in the input image and extracting a critical dimension (CD) value from a threshold with a Newton-Raphson algorithm.

10 . The method as claimed in claim 8 , wherein:

the DNN includes a plurality of down-sample layers,

the DNN uses at least one of a residual block structure, a dual residual block structure, a sum-fusion layer, a residual block first structure, a nearest-neighbor, bi-linear, or bi-cubic sampling method up-scaling, and a swish activation function.

11 . The method as claimed in claim 8 , wherein:

the DNN uses a different structure according to a semiconductor process to be modeled through architecture parameter adjustment, and

the architecture parameter adjustment includes at least one of an adjustment of a number of down-sample layers, an adjustment of a number of residual blocks, a size adjustment of a kernel in the residual block, a size adjustment of an input kernel according to a size of a rasterization filter, and an adjustment of a number of model parameters according to layout complexity.

12 . A semiconductor device patterning method, comprising:

acquiring an After Develop Inspection (ADI) image of a pattern of a sample;

extracting a contour image from the ADI image;

generating an input image by rasterizing the contour image;

obtaining an After Cleaning Inspection (ACI) image for the pattern of the sample after an etching process for the sample as an output image;

generating a predictive model through learning using a Deep Neural Network (DNN) with the input image and the output image;

predicting a pattern image of a semiconductor device after the etching process by using the predictive model;

determining whether the predicted pattern image after the etching process satisfies a set condition; and

forming a pattern on the semiconductor device through the etching process when the condition is satisfied.

13 . The method as claimed in claim 12 , further comprising automatically filtering and removing bad images from the acquiring of the ADI image to the generating of the input image.

14 . The method as claimed in claim 12 , further comprising generating a density map for a full-chip of the sample, and adding the density map as the input image to a channel.

15 . The method as claimed in claim 12 , wherein the DNN includes a masking layer that delimits or confines regions.

16 . The method as claimed in claim 12 , wherein:

the DNN includes a plurality of down-sample layers, and

the DNN uses at least one of a residual block structure, a dual residual block structure, a sum-fusion layer, a residual block first structure, a nearest-neighbor, bi-linear, or bi-cubic sampling method up-scaling, and a swish activation function.

17 . The method as claimed in claim 12 , wherein:

the DNN uses a different structure according to a semiconductor process to be modeled through architecture parameter adjustment,

the architecture parameter adjustment includes at least one of an adjustment of a number of down-sample layers, an adjustment of a number of residual blocks, a size adjustment of a kernel in the residual block, a size adjustment of an input kernel according to a size of a rasterization filter, and an adjustment of a number of model parameters according to layout complexity.