IP Library Granted Patent US 12672497
Granted Patent B2
US 12672497 · App. 17/386,554 · Granted Jun 30, 2026

Wafer with test structure and method of dicing wafer

Inventors: Wei-Ren Huang (Changhua County, TW); Chen-Hsiao Wang (Hsinchu City, TW); Kai-Kuang Ho (Hsinchu City, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H10P54/00H10P50/242H10P50/691H10P50/73H10P74/273
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Quick Facts
Patent No.
US 12672497
App. No.
17/386,554
Granted
Jun 30, 2026
Kind
B2
Abstract

A wafer with a test structure includes a wafer with a front side and a back side. A first die, a second die, a third die and a scribe line are disposed on the wafer. The scribe line is positioned between the dice. The first die includes a first dielectric layer and a first metal connection disposed within and on the first dielectric layer. A test structure and a dielectric layer are disposed on the scribe line, wherein the test structure is on the dielectric layer. Two first trenches are respectively disposed between the first dielectric layer and the dielectric layer and disposed at one side of the dielectric layer. Two second trenches penetrate the wafer, and each of the two second trenches respectively connects to a corresponding one of the two first trenches. A grinding tape covers the front side of the wafer and contacts the test structure.

Claims (17)

1 . A wafer with a test structure, comprising:

a wafer with a front side and a back side, wherein a first die, a second die, and a scribe line are disposed on the front side of the wafer, the scribe line is positioned between the first die and the second die, the first die comprises a first dielectric layer and a first metal connection which is disposed within and on the first dielectric layer;

a test structure and a dielectric layer disposed on the scribe line, wherein the test structure is disposed on the dielectric layer;

two first trenches, wherein one of the two first trenches is disposed between the first dielectric layer and the dielectric layer and at a first side of the test structure, and wherein the other one of the two first trenches is disposed at one side of the dielectric layer, at a second side of the test structure, the first side and the second side are opposite, and the first side and the second side are two sides of the same test structure;

two second trenches penetrating the wafer, wherein one of the two second trenches connects to the first trench disposed at the first side of the test structure, and the other one of the two second trenches connects to the first trench disposed at the second side of the test structure, and wherein in a sectional view taken along a line passing through the first die, the test structure, the second die, and the scribe line, the two second trenches do not connect to each other;

a photoresist covering and contacting the back side of the wafer, wherein openings within the photoresist correspond to the two second trenches, and sidewalls of each of the openings are aligned with sidewalls of a corresponding one of the two second trenches; and

a grinding tape covering the front side of the wafer and contacting the test structure.

2 . The wafer with a test structure of claim 1 , wherein the second die comprises a second metal connection and a second dielectric layer, the second metal connection is disposed within and on the second dielectric layer, and one of the two first trenches is disposed between the second dielectric layer and the dielectric layer.

3 . The wafer with a test structure of claim 2 , wherein the test structure is disposed between the first metal connection and the second metal connection.

4 . The wafer with a test structure of claim 1 , wherein a topmost surface of the first metal connection is aligned with a topmost surface of the test structure.

5 . The wafer with a test structure of claim 1 , wherein the first metal connection comprises a protective ring.

6 . The wafer with a test structure of claim 1 , wherein a sidewall of each of the two second trenches is substantially flat.

7 . The wafer with a test structure of claim 1 , wherein there is no delamination or crack on a sidewall of each of the two second trenches.

8 . The wafer with a test structure of claim 2 , wherein the test structure is not exposed through the two first trenches, and the first metal connection and the second metal connection are not exposed through the two first trenches.

9 . The wafer with a test structure of claim 2 , further comprising a protective layer covering the first metal connection and the second metal connection.

10 . The wafer with a test structure of claim 1 , wherein a depth of each of the two first trenches is 8 to 15 micrometers.

11 . The wafer with a test structure of claim 1 , wherein in the sectional view taken along the line passing through the first die, the test structure, the second die, and the scribe line, the two first trenches are disposed on the same scribe line.