IP Library Granted Patent US 12672498
Granted Patent B2
US 12672498 · App. 17/390,694 · Granted Jun 30, 2026

Method of manufacturing semiconductor structure

Inventors: Bo Hua Chen (Kaohsiung, TW); Yan Ting Shen (Kaohsiung, TW); Tsung Chi Wu (Kaohsiung, TW); Tai-Hung Kuo (Kaohsiung, TW)
Assignee: Advanced Semiconductor Engineering, Inc.
H10P54/00H10P34/42
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Quick Facts
Patent No.
US 12672498
App. No.
17/390,694
Granted
Jun 30, 2026
Kind
B2
Abstract

A method of manufacturing a semiconductor structure is provided. The method includes the following operations: providing a semiconductor substrate; performing a first cutting operation along a first set of cutting lines of the semiconductor substrate; and performing a second cutting operation along a second set of cutting lines of the semiconductor substrate later than performing the first cutting operation, wherein the second set of cutting lines are arranged interlacedly with the first set of cutting lines along a first direction.

Claims (10)

1 . A method of manufacturing a semiconductor structure, comprising:

providing a semiconductor substrate having an active surface;

scanning a first linear portion in an interior region of the semiconductor substrate by a laser beam along a first direction substantially parallel to the active surface of the semiconductor substrate;

scanning a second linear portion in the interior region of the semiconductor substrate by the laser beam along a second direction opposite to the first direction after scanning the first linear portion; and

scanning a third linear portion in the interior region of the semiconductor substrate by the laser beam along the first direction or the second direction after scanning the second linear portion, wherein the third linear portion is between the first linear portion and the second linear portion.

2 . The method as claimed in claim 1 , wherein the first linear portion, the second linear portion, and the third linear portion are scanned from the active surface of the semiconductor substrate.

3 . The method as claimed in claim 1 , wherein the semiconductor substrate comprises a plurality of device regions on the active surface, and the first linear portion, the second linear portion, and the third linear portion are free from overlapping the device regions in a direction substantially perpendicular to the active surface of the semiconductor substrate.

4 . The method as claimed in claim 1 , wherein the first linear portion, the second linear portion, and the third linear portion are at a substantially same elevation that is substantially parallel to the active surface of the semiconductor substrate.

5 . The method as claimed in claim 1 , wherein the first linear portion, the second linear portion, and the third linear portion are scanned by the laser beam along three different cutting lines.

6 . The method as claimed in claim 1 , further comprising scanning a fourth linear portion and a fifth linear portion in the interior region of the semiconductor substrate by the laser beam along a third direction and a fourth direction opposite to the third direction after scanning the third linear portion, the third direction and the fourth direction being substantially perpendicular to the first direction and substantially parallel to the active surface of the semiconductor substrate.