IP Library › Granted Patent US 12672523
Granted Patent B2
US 12672523 · App. 18/222,057 · Granted Jun 30, 2026

System and method for die crack detection in wafer-to-wafer bonding

Inventors: Jayavel Pachamuthu (San Jose, CA); Kirubakaran Periyannan (Santa Clara, CA); Daniel J. Linnen (Naperville, IL); Stephen Skala (Fremont, CA)
Assignee: Sandisk Technologies, Inc.
H10P74/277H10D1/68H10W42/00
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12672523
App. No.
18/222,057
Granted
Jun 30, 2026
Kind
B2
Abstract

In wafer-to-wafer bonding, a first die is bonded to a second die at a bonding interface. Various configurations of capacitors are placed along an inner portion of an edge seal of the bonded dies to detect a discontinuity in the bonding interface. These configurations include interdigitated capacitors, which can be horizontally or vertically oriented, parallel-digitated capacitors, and pillars forming a parameter around the dies with conductive portions offset from the pillar and extending inside the dies. Other configurations can be used.

Claims (29)

1 . An integrated circuit comprising:

a memory die;

a control die comprising control circuitry for the memory die, wherein the memory die and the control die are bonded together at a bonding interface;

an edge seal surrounding the memory die and the control die, wherein the edge seal comprises a plurality of rings perpendicular to the bonding interface, and wherein the plurality of rings comprises an inner seal ring, which is farther away than any other ring of the plurality of rings from a scribe line where the integrated circuit was diced; and

a plurality of interdigitated capacitors located in an inner portion of the inner seal ring;

wherein the plurality of interdigitated capacitors are perpendicular to the bonding interface;

wherein the plurality of interdigitated capacitors are configured to detect a discontinuity in the bonding interface between the memory die and the control die; and

wherein the plurality of interdigitated capacitors comprise a plurality of spaced apart, mating fingers.

2 . The integrated circuit of claim 1 , wherein the plurality of interdigitated capacitors are vertically positioned.

3 . The integrated circuit of claim 1 , wherein the plurality of interdigitated capacitors are horizontally positioned.

4 . The integrated circuit of claim 1 , wherein the plurality of interdigitated capacitors are located in the memory die.

5 . The integrated circuit of claim 1 , wherein the plurality of interdigitated capacitors are located in the control die.

6 . The integrated circuit of claim 1 , wherein the plurality of interdigitated capacitors are located in the memory die and the control die.

7 . The integrated circuit of claim 1 , wherein the control circuitry comprises complementary metal-oxide-semiconductor (CMOS) circuitry.

8 . An integrated circuit comprising:

a first die formed in a first silicon wafer;

a second die formed in a second silicon wafer, wherein the first and second silicon wafers and the first and second dies are bonded together at a bonding interface, thereby electrically coupling the first die to the second die;

an edge seal surrounding the first die and the second die, wherein the edge seal comprises a plurality of rings perpendicular to the bonding interface, and wherein the plurality of rings comprises an inner seal ring, which is farther away than any other ring of the plurality of rings from a scribe line where the integrated circuit was diced; and

means for detecting a discontinuity in the bonding interface between the first and second dies, wherein the means for detecting comprises a plurality of interdigitated capacitors comprising a plurality of spaced apart, mating fingers, wherein the plurality of interdigitated capacitors are located in an inner portion of the inner seal ring and are perpendicular to the bonding interface.

9 . In an integrated circuit comprising a memory die; a control die comprising control circuitry for the memory die, wherein the memory die and the control die are bonded together at a bonding interface; an edge seal surrounding the memory die and the control die, wherein the edge seal comprises a plurality of rings perpendicular to the bonding interface, and wherein the plurality of rings comprises an inner seal ring, which is farther away than any other ring of the plurality of rings from a scribe line where the integrated circuit was diced, and a plurality of interdigitated capacitors located in an inner portion of the inner seal ring, a method comprising:

receiving a voltage across the plurality of interdigitated capacitors; and

providing an indication of a discontinuity in the bonding interface between the memory die and the control die;

wherein the plurality of interdigitated capacitors are perpendicular to the bonding interface and comprise a plurality of spaced apart, mating fingers.

10 . The method of claim 9 , wherein the plurality of interdigitated capacitors are vertically positioned.

11 . The method of claim 9 , wherein the plurality of interdigitated capacitors are horizontally positioned.

12 . The method of claim 9 , wherein the plurality of interdigitated capacitors are located in the memory die.

13 . The method of claim 9 , wherein the plurality of interdigitated capacitors are located in the control die.

14 . The method of claim 9 , wherein the plurality of interdigitated capacitors are located in the memory die and the control die.

15 . The method of claim 9 , wherein the control circuitry comprises complementary metal-oxide-semiconductor (CMOS) circuitry.