Semiconductor device including a self-formed barrier metal layer

1 . A semiconductor device comprising:

a substrate;

an interconnect layer disposed over the substrate;

a metal line formed in the interconnect layer;

a dielectric layer disposed on the interconnect layer; and

a via contact formed in the dielectric layer and electrically connected to the metal line, one of the via contact and the metal line including a first metal material and a barrier metal layer disposed on the first metal material, the first metal material including an alloy which is a mixture of two metal elements, the barrier metal layer including one of the two metal elements,

wherein the semiconductor device further includes a first metal oxide layer that is disposed between the dielectric layer and the barrier metal layer of the metal line, and that is penetrated by the via contact, and

wherein a bottom surface of the first metal oxide layer is lower than a bottom surface of the dielectric layer.

2 . The semiconductor device according to claim 1 , wherein the two metal elements of the alloy are a relatively active metal element having a lower reduction potential and a relatively noble metal element having a higher reduction potential, the barrier metal layer including the relatively noble metal element of the alloy.

3 . The semiconductor device according to claim 2 , wherein the alloy of the first metal material is presented as A x B y , where A is the relatively active metal element, B is the relatively noble metal element, x is an integer ranging from 1 to 5, and y is another integer ranging from 1 to 9.

4 . The semiconductor device according to claim 2 , wherein the relatively active metal element includes one of aluminum, manganese, zirconium and chromium.

5 . The semiconductor device according to claim 2 , wherein the relatively noble metal element includes one of copper, ruthenium and cobalt.

6 . The semiconductor device according to claim 2 , further comprising:

another metal line which is formed in the interconnect layer and which includes a first metal material and a barrier metal layer disposed on the first metal material, the first metal material of the another metal line being the same as the first metal material of the one of the via contact and the metal line, materials of the barrier metal layer of the another metal line and the barrier metal layer of the one of the via contact and the metal line being the same; and

a second metal oxide layer which is formed in the interconnect layer and which covers an upper surface of the another metal line.

7 . The semiconductor device according to claim 1 , further comprising:

another metal line which is formed in the interconnect layer and which includes a hybrid metal structure, the hybrid metal structure including a first metal material that is located at lateral and bottom regions of the hybrid metal structure and a second metal material that is located at a central region of the hybrid metal structure, the first metal material of the hybrid metal structure being the same as the first metal material of the one of the via contact and the metal line.

8 . The semiconductor device according to claim 7 , wherein the second metal material includes one of copper, ruthenium and cobalt.

9 . The semiconductor device according to claim 1 , further comprising a barrier layer which is formed in the interconnect layer and which is sandwiched between the metal line and the interconnect layer.

10 . The semiconductor device according to claim 1 , further comprising a barrier layer which is formed in the dielectric layer and which is sandwiched between the via contact and the dielectric layer.

11 . The semiconductor device according to claim 1 , further comprising a conductive line which is disposed on the via contact, the conductive line being electrically connected to the metal line through the via contact,

wherein the metal line includes the first metal material and the barrier metal layer, and the conductive line includes a material identical to a material of the via contact.

12 . The semiconductor device according to claim 1 , further comprising a conductive line which is disposed on the via contact, the conductive line being electrically connected to the metal line through the via contact,

wherein the via contact includes the first metal material and the barrier metal layer, and the conductive line includes a material different from the first metal material of the via contact.

13 . The semiconductor device according to claim 1 , wherein the bottom surface of the first metal oxide layer interfaces a top surface of the barrier metal layer.

14 . A semiconductor device comprising:

a substrate;

an interconnect layer disposed over the substrate;

a metal line formed in the interconnect layer;

a dielectric layer disposed on the interconnect layer; and

a via contact formed in the dielectric layer and electrically connected to the metal line, one of the via contact and the metal line including a hybrid metal structure and a metal layer,

wherein the hybrid metal structure includes a first metal material located at lateral and bottom regions of the hybrid metal structure, and including an alloy which is a mixture of two metal elements, and

a second metal material located at a central region of the hybrid metal structure, and being different from the first metal material, wherein the metal layer is disposed on the first metal material of the hybrid metal structure of the metal line and laterally covers the second metal material, and

wherein a side surface of the second metal material has a direct interface with each of the first metal material and the metal layer.

15 . The semiconductor device according to claim 14 , further comprising a metal oxide layer disposed on the metal layer, the metal oxide layer including one of the two metal elements, the metal layer including the other one of the two metal elements.

16 . The semiconductor device according to claim 14 , wherein an upper surface of the second metal material is exposed from the metal oxide layer.

17 . The semiconductor device according to claim 14 , further comprising an etch stop layer disposed between the interconnect layer and the dielectric layer, a bottom surface of the etch stop layer interfacing a top surface of the second metal material which is connected to the side surface of the second metal material.

18 . A semiconductor device comprising:

a substrate;

an interconnect layer disposed over the substrate;

a metal line formed in the interconnect layer;

a metal-containing etch stop layer disposed on the interconnect layer;

a non-metallic etch stop layer disposed on and interfacing a top surface of the metal-containing etch stop layer;

a dielectric layer disposed on the non-metallic etch stop layer opposite to the metal-containing etch stop layer; and

a via contact formed in the dielectric layer and electrically connected to the metal line, one of the via contact and the metal line including a first metal material and a barrier metal layer disposed on the first metal material and being in contact with the metal-containing etch stop layer, the first metal material including an alloy which is a mixture of two metal elements, the barrier metal layer including one of the two metal elements.

19 . The semiconductor device according to claim 18 , wherein the via contact penetrates the metal-containing etch stop layer and the non-metallic etch stop layer, and is in direct contact with the barrier metal layer.

20 . The semiconductor device according to claim 18 , wherein an entirety of the interconnect layer is located directly above the substrate.