IP Library Granted Patent US 12672530
Granted Patent B2
US 12672530 · App. 17/715,876 · Granted Jun 30, 2026

Electronic package

Inventors: Hung-Yi Lin (Kaohsiung, TW); Cheng-Yuan Kung (Kaohsiung, TW)
Assignee: Advanced Semiconductor Engineering, Inc.
H10W20/20H10W90/00H10W74/15H10W90/724H10W90/734H10W90/792
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Quick Facts
Patent No.
US 12672530
App. No.
17/715,876
Granted
Jun 30, 2026
Kind
B2
Abstract

An electronic package is provided. The electronic package includes a processing component and a memory unit. The processing component has a side including a first region and a second region distinct from the first region. The memory unit is disposed over the first region. The first region is configured to provide interconnection between the processing component and the memory unit, and the second region is configured to provide external connection.

Claims (32)

1 . An electronic package, comprising:

a processing component having a first side comprising a first region and a second region distinct from the first region, wherein the processing component has a third region at a second side opposite to the first side;

a memory unit disposed over the first region, wherein the first region is configured to provide interconnection between the processing component and the memory unit, and the second region is configured to provide external connection;

a first connection structure on the second region and electrically connected to the processing component, wherein the first connection structure extends along a lateral side of the memory unit;

a second connection structure on the third region and electrically connected to the processing component, wherein a diameter of the second connection structure is greater than a diameter of the first connection structure; and

a carrier supporting the processing component, wherein the second connection structure passes through the carrier.

2 . The electronic package of claim 1 , wherein the memory unit covers the first region and does not cover the second region.

3 . The electronic package of claim 2 , wherein the first region separates the second region into two portions.

4 . The electronic package of claim 3 , wherein the second region surrounds the first region.

5 . The electronic package of claim 1 , wherein a digital signal is transmitted between the processing component and the memory unit, and between the first region and the second region of the processing component.

6 . The electronic package of claim 5 , wherein the third region is configured to receive a power into the processing component.

7 . The electronic package of claim 6 , wherein the processing component comprises an active surface and a passive surface opposite to the active surface, and the first region and the second region are closer to the active surface than to the passive surface.

8 . The electronic package of claim 1 , wherein the carrier comprises a voltage regulating element and a power path configured to transmit a power passing through the second connection structure, the voltage regulating element, and the processing component.

9 . An electronic package, comprising:

a processing component having a first surface and a second surface opposite to the first surface, wherein the processing component is configured to transmit a digital signal through the first surface and receive a power through the second surface;

a memory unit adjacent to the first surface of the processing component;

a first connection structure extending from the second surface toward the first surface and configured to transmit the power; and

a second connection structure on the first surface and configured to transmit the digital signal.

10 . The electronic package of claim 9 , wherein the second connection structure extends along at least two lateral sides of the memory unit.

11 . The electronic package of claim 9 , wherein the processing component comprises a first edge and a second edge, and the memory unit extends from the first edge toward the second edge.

12 . An electronic package, comprising:

a first carrier;

a second carrier disposed over the first carrier; and

an assembly structure disposed between the first carrier and the second carrier, the assembly structure comprising:

a processing unit configured to receive a power signal from the first carrier into the processing unit;

a storage unit stacked on the processing unit; and

a first connection structure extending along a lateral side of the storage unit and configured to transmit a non-power signal from the processing unit to the second carrier.

13 . The electronic device of claim 12 , wherein the assembly structure comprises:

a third carrier disposed between the processing unit and the first carrier; and

a second connection structure passing through the third carrier and configured to transmit the power signal.

14 . The electronic package of claim 13 , further comprising a protective element configured to encapsulate the assembly structure.

15 . The electronic package of claim 12 , further comprising a conductive structure extending along at least a lateral side of the assembly structure and connecting the first carrier and the second carrier.