Transistors with via-to-backside power rail spacers
A semiconductor structure includes a source/drain region; a frontside source/drain contact disposed on the source/drain region, a via-to-backside power rail disposed on the frontside source/drain contact and on a portion of the source/drain region, and a backside power rail connected to the via-to-backside power rail.
1 . A semiconductor structure, comprising:
a source/drain region;
a frontside source/drain contact disposed on the source/drain region;
a via-to-backside power rail disposed on the frontside source/drain contact and on a portion of the source/drain region;
a backside power rail connected to the via-to-backside power rail; and
an adhesion layer separating the via-to-backside power rail and the frontside source/drain contact.
2 . The semiconductor structure of claim 1 , wherein the via-to-backside power rail comprises a lower portion located on the backside power rail and an upper portion located on the frontside source/drain contact.
3 . The semiconductor structure of claim 2 , wherein the upper portion of the via-to-backside power rail and the frontside source/drain contact comprise a dual damascene metal structure.
4 . The semiconductor structure of claim 2 , further comprising the adhesion layer disposed between the lower portion and the upper portion of the via-to-backside power rail.
5 . The semiconductor structure of claim 4 , wherein the adhesion layer is a metal adhesion layer.
6 . The semiconductor structure of claim 4 , further comprising a dielectric spacer disposed on a sidewall of the upper portion of the via-to-backside power rail.
7 . The semiconductor structure of claim 1 , further comprising a silicide layer disposed between the frontside source/drain contact and the source/drain region.
8 . The semiconductor structure of claim 7 , wherein the silicide layer is further disposed between a portion of an upper portion of the via-to-backside power rail and the source/drain region.
9 . The semiconductor structure of claim 7 , wherein the adhesion layer is disposed on the via-to-backside power rail.
10 . The semiconductor structure of claim 1 , wherein the backside power rail is disposed in a backside interlayer dielectric layer.
11 . A semiconductor structure, comprising:
a first gate structure;
a second gate structure;
a sidewall spacer disposed on a portion of sidewalls of the first gate structure and the second gate structure;
a dielectric spacer disposed on the remaining portion of the sidewalls of the first gate structure and the second gate structure; and
a via-to-backside power rail disposed between the first gate structure and the second gate structure, the via-to-backside power rail having a lower portion separated from the first gate structure and the second gate structure by the sidewall spacer and an upper portion separated from the first gate structure and the second gate structure by the dielectric spacer.
12 . The semiconductor structure of claim 11 , further comprising a backside power rail disposed on the via-to-backside power rail.
13 . The semiconductor structure of claim 11 , further comprising an adhesion layer disposed between the lower portion and the upper portion of the via-to-backside power rail.
14 . The semiconductor structure of claim 13 , wherein the adhesion layer is a metal adhesion layer.
15 . The semiconductor structure of claim 11 , wherein the dielectric spacer is aligned with the sidewall spacer.
16 . A semiconductor structure, comprising:
a first source/drain region;
a second source/drain region;
a first frontside source/drain contact disposed on the first source/drain region;
a second frontside source/drain contact disposed on the second source/drain region;
a via-to-backside power rail disposed on the first frontside source/drain contact and on a portion of the first source/drain region;
a backside power rail connected to the via-to-backside power rail; and
an adhesion layer separating the via-to-backside power rail and the first frontside source/drain contact.
17 . The semiconductor structure of claim 16 , wherein the via-to-backside power rail comprises a lower portion located on the backside power rail and an upper portion located on the first frontside source/drain contact.
18 . The semiconductor structure of claim 17 , wherein the upper portion of the via-to-backside power rail and the first frontside source/drain contact comprise a dual damascene metal structure.
19 . The semiconductor structure of claim 16 , further comprising a silicide layer disposed between each of the first frontside source/drain contact and the first source/drain region and the second frontside source/drain contact and the second source/drain region.
20 . The semiconductor structure of claim 19 , wherein the adhesion layer is disposed on the via-to-backside power rail.