Enlarged shallow trench isolation for backside power
Semiconductor devices and methods of forming the same include a first semiconductor device in a first device region and a second semiconductor device in a second device region. A dielectric structure between the first device region and the second device region laterally extends part way underneath the first semiconductor device and the second semiconductor device. A buried power rail is under the dielectric structure. A conductive via penetrates the dielectric structure to connect the first semiconductor device to the buried power rail.
1 . A semiconductor device, comprising:
a first semiconductor device in a first device region;
a second semiconductor device in a second device region;
a dielectric structure between the first device region and the second device region, which laterally extends part way underneath the first semiconductor device and the second semiconductor device;
a first dielectric layer between the dielectric structure and the first semiconductor device, having an ‘L’-shaped cross-section;
a buried power rail under the dielectric structure; and
a conductive via that penetrates the dielectric structure to connect the first semiconductor device to the buried power rail.
2 . The semiconductor device of claim 1 , further comprising a second dielectric layer between the dielectric structure and the second semiconductor device.
3 . The semiconductor device of claim 2 , wherein the dielectric layer and the dielectric structure are formed from different dielectric materials.
4 . The semiconductor device of claim 2 , further comprising a layer of semiconductor material under the dielectric layer.
5 . The semiconductor device of claim 4 , wherein the layer of semiconductor material has a first edge that aligns with an edge of a channel layer of the first semiconductor device and has an opposite second edge that does not align with an edge of the channel layer of the first semiconductor device.
6 . The semiconductor device of claim 5 , wherein the dielectric structure is between the layer of semiconductor material and the conductive via.
7 . The semiconductor device of claim 1 , wherein the conductive via extends to a height above the first semiconductor device and makes electrical contact with a top and side surface of a source/drain structure of the first semiconductor device.
8 . The semiconductor device of claim 1 , further comprising:
back-end-of-line layers over the first semiconductor device and the second semiconductor device; and
a backside power distribution network under the buried power rail.
9 . The semiconductor device of claim 1 , wherein the first dielectric layer is on a first side surface of the first semiconductor device and not on a second side surface of the first semiconductor device, opposite to the first side surface.
10 . The semiconductor device of claim 1 , further comprising a shallow trench isolation structure on a side surface of the first dielectric device opposite to the first dielectric layer, the shallow trench isolation structure being in direct contact with the first semiconductor device.
11 . A semiconductor device, comprising:
a first semiconductor device in a first device region;
a second semiconductor device in a second device region;
a dielectric structure between the first device region and the second device region, which laterally extends part way underneath the first semiconductor device and the second semiconductor device;
a first dielectric layer between the dielectric structure and the first semiconductor device, having an ‘L’-shaped cross-section;
a buried power rail under the dielectric structure;
a conductive via that penetrates the dielectric structure to connect the first semiconductor device to the buried power rail; and
a back-end-of-line layer over the first semiconductor device and the second semiconductor device that includes a conductive via to connect to the second semiconductor device.
12 . The semiconductor device of claim 11 , further comprising a dielectric second layer between the dielectric structure and the second semiconductor device.
13 . The semiconductor device of claim 12 , wherein the dielectric layer and the dielectric structure are formed from different dielectric materials.
14 . The semiconductor device of claim 12 , further comprising a layer of semiconductor material under the dielectric layer.
15 . The semiconductor device of claim 14 , wherein the layer of semiconductor material has a first edge that aligns with an edge of a channel layer of the first semiconductor device and has an opposite second edge that does not align with an edge of the channel layer of the first semiconductor device.
16 . The semiconductor device of claim 15 , wherein the dielectric structure is between the layer of semiconductor material and the conductive via.
17 . The semiconductor device of claim 11 , wherein the conductive via extends to a height above the first semiconductor device and makes electrical contact with a top and side surface of a source/drain structure of the first semiconductor device.