Semiconductor devices including contact plugs having silicide layers and methods for fabricating the same

1 . A semiconductor device comprising:

an inter-layer dielectric layer disposed over a substrate;

a first contact plug structure coupled to a first active region of the substrate by vertically penetrating the inter-layer dielectric layer; and

a second contact plug structure coupled to a second active region of the substrate by vertically penetrating the inter-layer dielectric layer,

wherein the first contact plug structure includes:

a first metal silicide layer;

a first contact barrier layer disposed over the first metal silicide layer; and

a first contact plug disposed over the first contact barrier layer,

wherein the second contact plug structure includes:

a second metal silicide layer;

a second contact barrier layer disposed over the second metal silicide layer; and

a second contact plug disposed over the second contact barrier layer,

wherein the first metal silicide layer and the second metal silicide layer include different metal silicides,

wherein the first metal silicide layer has a U-shaped cross-section to be in contact with outer side surfaces of a lower portion of the first contact barrier layer,

wherein outer side surfaces of the first metal silicide layer are in contact with the substrate,

wherein the second metal silicide layer has a pad shape in contact with a bottom surface of the second contact barrier layer, and

wherein outer side surfaces of the second contact barrier layer are not surrounded by the second metal silicide layer.

2 . The semiconductor device of claim 1 ,

wherein the first metal silicide layer includes at least one of cobalt silicide, molybdenum silicide, and titanium carbon silicide, and

wherein the second metal silicide layer includes either titanium silicide or niobium silicide.

3 . The semiconductor device of claim 1 , further comprising a metal layer disposed between the first metal silicide layer and the first contact barrier layer,

wherein the metal layer and the second metal silicide layer contain a same metal.

4 . The semiconductor device of claim 3 , wherein the first metal silicide layer is in contact with bottom and side surfaces of the metal layer.

5 . The semiconductor device of claim 1 , further comprising a third contact plug structure coupled to a third region of the substrate,

wherein the third contact plug structure includes:

a lower contact plug between bit line structures and coupled to a source region of the substrate;

a third metal silicide layer disposed over the lower contact plug;

a third contact barrier layer disposed over the third metal silicide layer;

a third contact plug disposed over the third metal silicide layer; and

a capacitor structure disposed over the third contact plug, and

wherein the third metal silicide layer includes a same metal silicide as the second metal silicide layer.

6 . The semiconductor device of claim 1 , wherein side surfaces of a lower portion of the second contact barrier layer are in contact with the substrate.

7 . A semiconductor device comprising:

a first contact plug structure disposed in a first region of a substrate;

a second contact plug structure disposed in a second region of the substrate; and

a cell contact plug structure between bit line structures disposed in a cell region of the substrate,

wherein the first contact plug structure includes a first metal silicide layer, a first contact barrier layer, and a first contact plug, which are sequentially stacked,

wherein the second contact plug structure includes a second metal silicide layer, a second contact barrier layer, and a second contact plug, which are sequentially stacked,

wherein the cell contact plug structure includes a lower contact plug coupled to the cell region of the substrate, a cell metal silicide layer, a cell contact barrier layer, a cell contact plug, and a capacitor structure, which are sequentially stacked,

wherein the first metal silicide layer and the second metal silicide layer include different metals,

wherein the second metal silicide layer and the cell metal silicide layer include a same metal,

wherein the cell contact silicide layer is disposed at a higher level than the first and second metal silicide layers.

8 . The semiconductor device of claim 7 , further comprising a metal layer disposed between the first metal silicide layer and the first contact barrier layer,

wherein the metal layer, the second metal silicide layer, and the cell metal silicide layer contain the same metal,

wherein the first metal silicide layer is in contact with outer side surfaces of a lower portion of the first contact barrier layer,

wherein outer side surfaces of the first metal silicide layer are in contact with the substrate,

wherein the second metal silicide layer has a pad shape in contact with a bottom surface of the second contact barrier layer, and

wherein side surfaces of the second contact barrier layer are not surrounded by the second metal silicide layer.

9 . The semiconductor device of claim 8 ,

wherein bottom and side surfaces of the metal layer are in contact with the first metal silicide layer, and

wherein a top surface of the metal layer is in contact with the first contact barrier layer.

10 . The semiconductor device of claim 7 , wherein the first metal silicide layer has a horizontal withed wider than the second metal silicide layer and a vertical height greater than the second metal silicide layer.

11 . The semiconductor device of claim 1 ,

wherein the substrate includes:

a first epitaxial grown region in the first active region in which the first metal silicide layer is disposed; and

a second epitaxial grown region in the second active region in which the second metal silicide layer is disposed.

12 . A semiconductor device comprising:

a substrate with a first transistor area and a second transistor area;

a first gate structure and a first contact plug structure in the first transistor area; and

a second gate structure and a second contact plug structure in the second transistor area,

wherein the first contact plug structure includes:

a first metal silicide layer in the substrate;

a first contact barrier layer over the first metal silicide layer; and

a first contact plug over the first contact barrier layer,

wherein the second contact plug structure includes:

a second metal silicide layer in the substrate;

a second contact barrier layer over the second metal silicide layer; and

a second contact plug over the second contact barrier layer,

wherein:

the first metal silicide layer surrounds a bottom and side surfaces of a lower portion of the first contact barrier layer,

outer side surfaces of the first metal silicide layer are in contact with the substrate,

the second metal silicide layer is in contact with a bottom of the second contact barrier layer, and

outer side surfaces of a lower portion of the second contact barrier layer are in contact with the substrate.

13 . The semiconductor device of claim 12 , further comprising:

a metal layer between the first metal silicide layer and the first contact barrier layer,

wherein:

the metal layer does not surround the contact barrier layer,

side surfaces of the metal layer are in contact with and surrounded by the first metal silicide layer, and

the bottom of the first contact barrier layer is in contact with the metal layer.

14 . The semiconductor device of claim 12 ,

wherein a top end of the first metal silicide layer is higher than a top portion of the second metal silicide layer.

15 . The semiconductor device of claim 14 ,

wherein the top portion of the second metal silicide layer is lower than and spaced apart from a surface of the substrate.

16 . The semiconductor device of claim 12 ,

wherein the substrate includes:

a first epitaxial grown region in the first transistor area in which the first metal silicide layer is disposed; and

a second epitaxial grown region in the second transistor area in which the second metal silicide layer is disposed.

17 . The semiconductor device of claim 12 , further comprising:

a cell structure in a cell area of the substrate,

wherein the cell structure includes:

a source region and a drain region;

a bit line structure including a bit line contact plug coupled to the drain region;

a lower contact plug coupled to the source region,

a cell contact silicide layer over the lower contact plug;

a cell contact barrier layer over the cell contact silicide layer;

a cell contact plug over the cell contact barrier layer; and

a capacitor structure over the cell contact plug structure.

18 . The semiconductor device of claim 17 ,

wherein the cell contact silicide layer is positioned at a higher level than the first and second metal silicide layers.

19 . The semiconductor device of claim 18 ,

wherein the second contact silicide layer and the cell contact silicide layer include a same metal.

20 . The semiconductor device of claim 12 ,

wherein a top end of the first metal silicide layer is lower than the first gate dielectric layer.