IP Library Granted Patent US 12672544
Granted Patent B2
US 12672544 · App. 17/911,063 · Granted Jun 30, 2026

Semiconductor device

Inventors: Daichi Niwa (Kyoto, JP); Koshun Saito (Kyoto, JP)
Assignee: ROHM CO., LTD.
H10W42/121H10W70/417H10W70/457H10W70/465H10W70/481H10W74/111H10W72/07552H10W72/527H10W72/5363H10W72/5524H10W72/59H10W72/952H10W90/756
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Quick Facts
Patent No.
US 12672544
App. No.
17/911,063
Granted
Jun 30, 2026
Kind
B2
Abstract

A semiconductor device includes a substrate, a semiconductor element, a connection pad, a plated layer, a wire, and an encapsulation resin. The substrate includes a main surface. The semiconductor element is mounted on the main surface and includes a main surface electrode. The connection pad is formed of Cu, arranged with respect to the substrate, separated from the substrate, and includes a connection surface. The plated layer is formed of Ni and partially covers the connection surface. The wire is formed of Al and bonded to the main surface electrode and the plated layer. The encapsulation resin encapsulates the semiconductor element, the connection pad, the plated layer, and the wire.

Claims (33)

1 . A semiconductor device, comprising:

a substrate including a main surface;

a semiconductor element mounted on the main surface and including a main surface electrode oriented in the same direction as the main surface;

a connection pad formed of Cu, separated from the substrate in a first direction that is parallel to the main surface, and including a connection surface oriented in the same direction as the main surface;

a plated layer formed of Ni and partially covering the connection surface;

a wire formed of Al and including a first end bonded to the main surface electrode and a second end bonded to the plated layer; and

an encapsulation resin encapsulating the semiconductor element, the connection pad, the plated layer, and the wire, wherein

the connection surface includes a covered region that is covered by the plated layer and an exposed region that is exposed from the plated layer, and

the covered region is located between a first part of the exposed region and a second part of the exposed region in the first direction when viewed from a thickness direction perpendicular to the main surface.

2 . The semiconductor device according to claim 1 , wherein

the main surface electrode includes a control electrode and a drive electrode,

the connection pad includes a control pad and a drive pad that are separated from the substrate in the first direction that is parallel to the main surface and separated from each other in a second direction, the second direction being parallel to the main surface and orthogonal to the first direction, and

the wire includes a control wire connecting the control electrode and the control pad and a drive wire connecting the drive electrode and the drive pad.

3 . The semiconductor device according to claim 2 , wherein the control wire has a smaller diameter than the drive wire.

4 . The semiconductor device according to claim 3 , wherein

the diameter of the control wire is 40 μm or greater and 100 μm or less, and

the diameter of the drive wire is 200 μm or greater and 600 μm or less.

5 . The semiconductor device according to claim 2 , wherein

the control wire includes a bonding portion bonded to the control pad and formed on a plated layer of the control pad, and

the drive wire includes a bonding portion bonded to the drive pad, formed on a plated layer of the drive pad, and extending to the connection surface of the drive pad.

6 . The semiconductor device according to claim 5 , wherein the bonding portion of the drive wire at a region bonded to an upper surface of the plated layer has an area that is greater than or equal to a cross sectional area of the drive wire.

7 . The semiconductor device according to claim 1 , wherein the wire is bonded to the connection pad by ultrasonic bonding.

8 . The semiconductor device according to claim 1 , wherein

the semiconductor element includes a back surface electrode faced away from the main surface electrode,

the substrate is formed of Cu, and

the back surface electrode is connected to the substrate by solder.

9 . The semiconductor device according to claim 1 , wherein the plated layer is a rough-surface plated layer having a rougher surface than the connection surface of the connection pad.

10 . The semiconductor device according to claim 1 , wherein when viewed from the thickness direction, the covered region is located between a third part of the exposed region and a fourth part of the exposed region in a second direction parallel to the main surface and perpendicular to the first direction.

11 . The semiconductor device according to claim 10 , wherein when viewed from the thickness direction, the covered region is surrounded by the exposed region.

12 . The semiconductor device according to claim 2 , an area of the covered region of the control pad is smaller than an area of the covered region of the drive pad.

13 . The semiconductor device according to claim 5 , wherein the bonding portion of the drive wire bonded to the drive pad includes:

a first bonding portion bonded to the upper surface of the plated layer, and

a second bonding portion bonded to at least one of the exposed regions of the drive pad.