IP Library Granted Patent US 12672546
Granted Patent B2
US 12672546 · App. 18/182,824 · Granted Jun 30, 2026

Semiconductor device and method for manufacturing

Inventors: Aya Murayoshi (Yokohama Kanagawa, JP); Kazushiro Nomura (Kawasaki Kanagawa, JP)
Assignees: Kabushiki Kaisha Toshiba; Toshiba Electronic Devices & Storage Corporation
H10W42/121H10D30/668H10W20/0698H10W20/484
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12672546
App. No.
18/182,824
Granted
Jun 30, 2026
Kind
B2
Abstract

A semiconductor device includes a first conductive layer, a semiconductor layer, first to second control electrodes, and first to second electrode pads. The first conductive layer includes first to second conductive regions. The second conductive region is thinner than the first conductive region. The semiconductor layer is located on the first conductive layer, and includes first to fifth semiconductor regions. The first control electrode faces the first, second, and third semiconductor regions via a first insulating film. The second control electrode faces the first, fourth, and fifth semiconductor regions via a second insulating film. The first electrode pad is located above the semiconductor layer and electrically connected with the third semiconductor region. The second electrode pad is located above the semiconductor layer and electrically connected with the fifth semiconductor region. At least a portion of the first conductive region is positioned below the first and second electrode pads.

Claims (71)

1 . A semiconductor device, comprising:

a first conductive layer including a first conductive region and a second conductive region, an unevenness being provided in at least one of an upper surface or a lower surface of the first conductive layer, the second conductive region being thinner than the first conductive region;

a semiconductor layer located on the first conductive layer, the semiconductor layer including

a first semiconductor region of a first conductivity type,

a second semiconductor region located on a portion of the first semiconductor region, the second semiconductor region being of a second conductivity type,

a third semiconductor region located on the second semiconductor region, the third semiconductor region being of the first conductivity type,

a fourth semiconductor region located on an other portion of the first semiconductor region, the fourth semiconductor region being of the second conductivity type, and

a fifth semiconductor region located on the fourth semiconductor region, the fifth semiconductor region being of the first conductivity type;

a first control electrode facing the first, second, and third semiconductor regions via a first insulating film;

a second control electrode facing the first, fourth, and fifth semiconductor regions via a second insulating film;

a first electrode pad located above the semiconductor layer and electrically connected with the third semiconductor region; and

a second electrode pad located above the semiconductor layer and electrically connected with the fifth semiconductor region,

at least a portion of the first conductive region being positioned below the first and second electrode pads,

the first control electrode being arranged with the second and third semiconductor regions in a second direction, the first conductive region including a protruding portion protruding in a first direction relative to the second conductive region, the protruding portion being arranged with the first electrode pad in the first direction perpendicular to an upper surface of the semiconductor layer, a length of the protruding portion along the first direction being longer than the length of the first control electrode along the first direction, the second direction being perpendicular to the first direction.

2 . The device according to claim 1 , wherein

the first conductive region is continuous from a region below the first electrode pad to a region below the second electrode pad.

3 . The device according to claim 1 , wherein

an area in which the first conductive region is located surrounds the first and second electrode pads in a plane perpendicular to the first direction.

4 . The device according to claim 1 , wherein

the semiconductor layer includes:

a first semiconductor part located on the first conductive region; and

a second semiconductor part located on the second conductive region, and the first semiconductor part is thinner than the second semiconductor part.

5 . The device according to claim 4 , wherein

the second conductive region is thinner than the second semiconductor part.

6 . The device according to claim 5 , wherein

the first semiconductor part is thinner than the first conductive region.

7 . The device according to claim 1 , wherein

the second conductive region does not overlap the first and second electrode pads in the first direction.

8 . The device according to claim 1 , wherein

a plurality of the first electrode pads is provided,

a plurality of the second electrode pads is provided, and

the second conductive region is positioned below a region between one of the first electrode pads and an other one of the first electrode pads and below a region between one of the second electrode pads and an other one of the second electrode pads.

9 . A method for manufacturing a semiconductor device, the method comprising:

preparing a semiconductor wafer, the semiconductor wafer including

a semiconductor layer including

a first semiconductor region of a first conductivity type,

a second semiconductor region located on a portion of the first semiconductor region, the second semiconductor region being of a second conductivity type,

a third semiconductor region located on the second semiconductor region, the third semiconductor region being of the first conductivity type,

a fourth semiconductor region located on an other portion of the first semiconductor region, the fourth semiconductor region being of the second conductivity type, and

a fifth semiconductor region located on the fourth semiconductor region, the fifth semiconductor region being of the first conductivity type,

a first control electrode facing the first, second, and third semiconductor regions via a first insulating film,

a second control electrode facing the first, fourth, and fifth semiconductor regions via a second insulating film,

a first electrode pad located above the semiconductor layer and electrically connected with the third semiconductor region, and

a second electrode pad located above the semiconductor layer and electrically connected with the fifth semiconductor region, the first control electrode being arranged with the second and third semiconductor regions in a second direction, the first conductive region including a protruding portion protruding in a first direction relative to the second conductive region, the protruding portion being arranged with the first electrode pad in the first direction perpendicular to an upper surface of the semiconductor layer, a length of the protruding portion along the first direction being longer than the length of the first control electrode along the first direction, the second direction being perpendicular to the first direction;

etching a lower surface side of the semiconductor layer to form a first semiconductor part and a second semiconductor part in the semiconductor layer, the second semiconductor part being thicker than the first semiconductor part, at least a portion of the first semiconductor part being positioned below the first and second electrode pads; and

forming a first conductive layer at the lower surface side of the semiconductor layer,

the first conductive layer including

a first conductive region positioned under the first semiconductor part, and

a second conductive region positioned under the second semiconductor part, the second conductive region being thinner than the first conductive region.

10 . The device according to claim 1 , wherein

the semiconductor layer including a recess recessed upward from a lower surface of the semiconductor layer, the recess is arranged with the first electrode pad in the first direction,

a portion of the first conductive region is provided in the recess, and

a length of the recess along the first direction is longer than the length of the first control electrode along the first direction.

11 . A semiconductor device, comprising:

a first conductive layer including a first conductive region and a second conductive region, an unevenness being provided in at least one of an upper surface or a lower surface of the first conductive layer, the second conductive region being thinner than the first conductive region;

a semiconductor layer located on the first conductive layer, the semiconductor layer including

a first semiconductor region of a first conductivity type,

a second semiconductor region located on a portion of the first semiconductor region, the second semiconductor region being of a second conductivity type,

a third semiconductor region located on the second semiconductor region, the third semiconductor region being of the first conductivity type,

a fourth semiconductor region located on an other portion of the first semiconductor region, the fourth semiconductor region being of the second conductivity type, and

a fifth semiconductor region located on the fourth semiconductor region, the fifth semiconductor region being of the first conductivity type;

a first control electrode facing the first, second, and third semiconductor regions via a first insulating film;

a second control electrode facing the first, fourth, and fifth semiconductor regions via a second insulating film;

a first electrode pad located above the semiconductor layer and electrically connected with the third semiconductor region; and

a second electrode pad located above the semiconductor layer and electrically connected with the fifth semiconductor region,

at least a portion of the first conductive region being positioned below the first and second electrode pads,

the first conductive region including a protruding portion protruding in a first direction relative to the second conductive region, the protruding portion being arranged with the first electrode pad in the first direction perpendicular to an upper surface of the semiconductor layer, an area of the protruding portion in a plane perpendicular to a first direction being larger than an area of the first electrode pad in the plane.

12 . The device according to claim 11 , wherein

the semiconductor layer including a recess recessed upward from a lower surface of the semiconductor layer, the recess is arranged with the first electrode pad in the first direction,

a portion of the first conductive region is provided in the recess, and

an area of the recess in the plane is larger than the area of the first electrode pad in the plane.