Light sensor for package intrusion detection
View Patent ↗Some embodiments relate to an integrated device including a first thin film transistor (TFT) arranged over a substrate; a second TFT arranged over the substrate; a metal barrier layer arranged over the second TFT, where the metal barrier layer is configured to block incident radiation from reaching the second TFT; a Fresnel lens arranged over the first TFT, where the Fresnel lens is configured to focus incident radiation towards the first TFT; and where the first TFT and the second TFT are configured to be coupled to a differential amplifier, the differential amplifier being operable to detect the incident radiation by comparison of a first leakage current from the first TFT to a second leakage current from the second TFT.
1 . A method of forming an integrated device, comprising:
patterning a first dielectric layer formed over a substrate to form a first gate opening and a second gate opening;
forming a first gate within the first gate opening and a second gate within the second gate opening;
forming a first channel over the first gate and the second gate;
forming source/drain terminals within a second dielectric layer on a top surface of the first channel;
forming a blocking layer over the second dielectric layer and directly above the first gate;
forming a lens material over the second dielectric layer and directly above the second gate; and
performing one or more etching processes on the lens material to form a Fresnel lens over the first channel, the Fresnel lens having a focal point over a bottom surface of the first channel.
2 . The method of claim 1 , further comprising:
forming a capping layer over the first channel before forming the source/drain terminals, wherein the source/drain terminals extend along sidewalls of the capping layer, and wherein the focal point of the Fresnel lens is between a top surface of the capping layer and a bottom surface of the first channel.
3 . The method of claim 2 , wherein the source/drain terminals extend over the capping layer.
4 . The method of claim 1 , wherein the blocking layer is formed in a third dielectric layer, and has a top surface level with a top surface of the third dielectric layer, and wherein the lens material is formed on the top surface of the third dielectric layer.
5 . The method of claim 1 , further comprising:
forming a differential amplifier over the substrate, the differential amplifier having a first input and a second input; and
forming an interconnect structure coupling a first source/drain terminal of the source/drain terminals to the first input and a second source/drain terminal of the source/drain terminals to the second input.
6 . The method of claim 1 , wherein the source/drain terminals extend over the first gate.
7 . A method of forming an integrated device, comprising:
forming a first wire level over a substrate, the first wire level comprising a first wire and a second wire;
forming a first gate over the first wire and a second gate over the second wire, wherein the first gate and the second gate are separated by a first dielectric layer, and wherein the first gate has a first width;
forming a first gate dielectric layer over the first gate and the second gate;
forming a first channel layer over the first gate and the second gate;
forming source/drain terminals on a top surface of the first channel layer, wherein a first set of source/drain terminals over the first gate have first sidewalls facing away from the first gate that are separated by a first distance that is greater than the first width;
forming a blocking layer over the source/drain terminals and directly above the first gate, wherein the blocking layer has a second width that is greater than the first distance; and
forming a Fresnel lens over the first channel layer and the second gate, the Fresnel lens having a focal point over a bottom surface of the first channel layer.
8 . The method of claim 7 , further comprising forming a second wire level over the source/drain terminals before forming the blocking layer, wherein the second wire level comprises wires coupled to the source/drain terminals.
9 . The method of claim 7 , wherein the first set of source/drain terminals have second sidewalls facing a center of the first gate that are separated by a second distance that is less than the first width.
10 . The method of claim 7 , wherein after the Fresnel lens is formed, the Fresnel lens has a bottom surface at a first height above the first gate and the second gate, and the blocking layer has a bottom surface at a second height above the first gate and the second gate, and wherein the first height is greater than the second height.
11 . The method of claim 7 , wherein forming the blocking layer further comprises:
forming a dielectric layer over the source/drain terminals;
etching an opening in the dielectric layer spanning past first sidewalls of the first set of source/drain terminals;
filling the opening with a metal material; and
removing portions of the metal material extending past the opening.
12 . The method of claim 11 , wherein after the blocking layer is formed, the blocking layer has a sidewall between the first gate and the second gate.
13 . The method of claim 7 , further comprising forming a capping layer on the first channel layer.
14 . The method of claim 13 , wherein forming the source/drain terminals further comprises:
forming a dielectric layer over the capping layer;
etching openings through the dielectric layer and the capping layer, exposing an upper surface of the first channel layer;
depositing a source/drain material into the openings; and
removing portions of the source/drain material above an upper surface of the dielectric layer.
15 . The method of claim 13 , wherein the source/drain terminals are spaced from the blocking layer in a vertical direction by a dielectric layer.
16 . A method of forming an integrated device, comprising:
forming a first gate and a second gate over a substrate, wherein the first gate and the second gate are spaced in a first direction;
forming a first gate dielectric over the first gate and the second gate;
forming a first channel layer over the first gate dielectric, the first channel layer extending from the first gate to the second gate in the first direction;
forming a capping layer over the first channel layer, the capping layer extending from the first gate to the second gate in the first direction;
forming a first set of source/drain terminals overlying the first gate and a second set of source/drain terminals overlying the second gate;
forming a blocking layer over the first gate and the first set of source/drain terminals, wherein the blocking layer is spaced from the first gate and the first set of source/drain terminals in a second direction perpendicular to the first direction; and
forming a Fresnel lens over the second gate and the second set of source/drain terminals, wherein the Fresnel lens is spaced from the blocking layer in the first direction and the second direction.
17 . The method of claim 16 , wherein after the first set of source/drain terminals and the second set of source/drain terminals are formed, the first gate extends from a first source/drain terminal of the first set to a second source/drain terminal of the first set in the first direction.
18 . The method of claim 17 , wherein after the blocking layer is formed, the first source/drain terminal has a first sidewall facing away from the first gate and towards a first sidewall of the blocking layer, and the second source/drain terminal has a second sidewall facing away from the first gate and towards a second sidewall of the blocking layer that is opposite the first sidewall of the blocking layer.
19 . The method of claim 16 , wherein the first gate dielectric extends from the first gate to the second gate in the first direction and covers top surfaces of the first gate and the second gate.
20 . The method of claim 16 , wherein the blocking layer is formed in a first dielectric layer and wherein the Fresnel lens is formed over the first dielectric layer.