Package structure and manufacturing method thereof
A package structure includes a redistribution structure, a first conductive portion, a second conductive portion and a third conductive portion. The redistribution structure includes a first conductive pad and a second conductive pad. The first conductive portion is electrically connected with the first conductive pad. The second conductive portion is electrically connected with the second conductive pad. The first conductive portion at least partially overlaps the second conductive portion. The third conductive portion and the second conductive portion are located at the same layer. The third conductive portion does not overlap any conductive portion which is located at the same layer as the first conductive portion.
1 . A package structure, comprising:
a first circuit;
a second circuit located above the first circuit;
a redistribution structure located above the first circuit and comprising a first conductive pad and a second conductive pad;
a dielectric layer located above the redistribution structure, wherein the dielectric layer is made of a material including silicon nitride or titanium oxide;
a first conductive portion electrically connected to the first conductive pad;
a second conductive portion electrically connected to the second conductive pad, wherein the first conductive portion at least partially overlaps the second conductive portion;
a third conductive portion located at the same layer as the second conductive portion, wherein the second conductive portion and the third conductive portion are located above the dielectric layer, wherein the third conductive portion does not overlap any conductive portion located at the same layer as the first conductive portion;
a chip disposed on the second circuit and electrically connected with the redistribution structure; and
a first patterned material layer, wherein the first circuit is located above the first patterned material layer, wherein the first circuit does not overlap the first conductive pad and the second conductive pad, and wherein the first circuit overlaps the second circuit.
2 . The package structure of claim 1 , wherein the dielectric layer is located between the first conductive portion and the second conductive portion, wherein the first conductive portion, the dielectric layer and the second conductive portion form a capacitor.
3 . The package structure of claim 2 , wherein an area of a surface of the second conductive portion facing the dielectric layer is different from an area of a surface of the third conductive portion facing the dielectric layer.
4 . The package structure of claim 1 , further comprising:
a conductive pillar located in the dielectric layer and electrically connected to the first conductive portion and the second conductive portion, wherein the dielectric layer is located between the first conductive portion and the second conductive portion.
5 . The package structure of claim 4 , further comprising:
a first resistance line electrically connected between the second conductive portion and the second conductive pad.
6 . The package structure of claim 5 , further comprising:
a second resistance line electrically connected to the third conductive portion, wherein the second resistance line is located at the same layer as the third conductive portion, and the second resistance line does not overlap any conductive portion located at the same layer as the first conductive portion.
7 . The package structure of claim 6 , wherein a length of the first resistance line is different from a length of the second resistance line.
8 . The package structure of claim 4 , further comprising:
a first inductive coil electrically connected between the second conductive portion and the second conductive pad.
9 . The package structure of claim 8 , further comprising:
a second inductive coil electrically connected to the third conductive portion, wherein the second inductive coil is located at the same layer as the third conductive portion, and the second inductive coil does not overlap any conductive portion located at the same layer as the first conductive portion.
10 . The package structure of claim 9 , wherein the number of turns of the first inductive coil is different from the number of turns of the second inductive coil.
11 . The package structure of claim 1 , further comprising a second patterned material layer, a third patterned material layer, a fourth patterned material layer and a fifth patterned material layer, wherein the second patterned material layer, the third patterned material layer, and the fourth patterned material layer are located between the dielectric layer and the first patterned material layer.
12 . The package structure of claim 11 , wherein the first conductive pad, the second conductive pad, and at least a portion of the second circuit are located in the fifth patterned material layer.
13 . The package structure of claim 1 , wherein the redistribution structure is located between the dielectric layer and the first circuit, wherein the dielectric layer does not overlap the second circuit.
14 . A manufacturing method of a package structure, comprising:
forming a first circuit and a first patterned material layer on a glass carrier, wherein the first circuit is located above the first patterned material layer;
forming a second circuit located above the first circuit;
forming a redistribution structure located above the first circuit and comprising a first conductive pad and a second conductive pad;
forming a first conductive portion on the glass carrier:
wherein the first conductive portion is electrically connected to the first conductive pad,
wherein the first circuit does not overlap the first conductive pad and the second conductive pad,
wherein the first circuit overlaps the second circuit;
forming a dielectric layer located above the redistribution structure, wherein the dielectric layer is made of a material including silicon nitride or titanium oxide;
forming a second conductive portion electrically connected to the second conductive pad and a third conductive portion located at the same layer as the second conductive portion, wherein the first conductive portion at least partially overlaps the second conductive portion, and the third conductive portion does not overlap any conductive portion located at the same layer as the first conductive portion,
wherein the second conductive portion and the third conductive portion are located above the dielectric layer; and
disposing a chip on the second circuit, wherein the chip is electrically connected with the redistribution structure.
15 . The method of claim 14 , wherein forming the redistribution structure and the first conductive portion on the glass carrier is performed such that the first conductive portion, the first conductive pad and the second conductive pad are located at the same layer.
16 . The method of claim 14 , wherein forming the redistribution structure on the glass carrier is performed such that the first conductive pad is separated from the second conductive pad.
17 . The method of claim 14 , wherein forming the dielectric layer on the redistribution structure and the first conductive portion prior to forming the second conductive portion and the third conductive portion such that the first conductive portion, the dielectric layer and the second conductive portion form a capacitor.
18 . The method of claim 14 , further comprising:
forming a conductive pillar in the dielectric layer such that the conductive pillar is electrically connected to the first conductive portion and the second conductive portion.