Package substrate with power delivery network

1 . A semiconductor package substrate comprising:

a core layer positioned between a top metallization layer and a bottom metallization layer;

a plurality of plated through hole vias comprising a first plated through hole via and a second plated through hole via;

the first plated through hole via comprising a first top recess step;

a substrate segment, wherein the substrate segment separates the first and second plated through hole vias; and

a top passive device recess comprising the first recess step and a top recess portion of the substrate segment, wherein the top passive device recess is positioned between the first plated through hole via and the second plated through hole via,

wherein a first passive device is positioned in the top passive device recess and a second passive device is positioned in a bottom passive device recess,

wherein the first passive device and the second passive device are disposed at least partially in the first plated through hole via and the second plated through hole via,

wherein the top passive device recess and the bottom passive device recess are positioned vertically above one another in the core layer.

2 . The semiconductor package substrate of claim 1 , wherein the second plated through hole via comprises a second top recess step and the top passive device recess further comprises the second top recess step.

3 . The semiconductor package substrate of claim 1 , further comprising a first top contact pad and a second top contact pad in the top metallization layer, wherein the first top contact pad is positioned overlapping and coupled to a first end portion of the first passive device positioned in the top passive device recess and the second contact pad is positioned overlapping and coupled to a second end portion of the first passive device.

4 . The semiconductor package substrate of claim 3 , wherein the first top contact pad is positioned overlapping and coupled to the first plated through hole via and the second top contact pad is positioned overlapping and coupled to the second plated through hole via.

5 . The semiconductor package substrate of claim 2 , wherein the first plated through hole via further comprises a first bottom recess step and the second plated through hole via further comprises a second bottom recess step, and wherein the bottom passive device recess comprises the first bottom recess step, the second bottom recess step, and a bottom recess portion of the substrate segment.

6 . The semiconductor package substrate of claim 5 , further comprising a bottom metallization layer comprising a first bottom contact pad and a second bottom contact pad, wherein the first bottom contact pad is positioned overlapping and coupled to a first end portion of a bottom passive device positioned in the bottom passive device recess and the second bottom contact pad is positioned overlapping and coupled to a second end portion of the bottom passive device.

7 . The semiconductor package substrate of claim 6 , wherein the first bottom contact pad is positioned overlapping and coupled to the first plated through hole via and the second bottom contact pad is positioned overlapping and coupled to the second plated through hole via.

8 . The semiconductor package substrate of claim 1 , wherein the first plated through hole via comprises a first conductive periphery surrounding a first non-conductive central column, and wherein the second plated through hole via comprises a second conductive periphery surrounding a second non-conductive central column.

9 . The semiconductor package substrate of claim 1 , wherein the first plated through hole via has a greater diameter than the second plated through hole via, and wherein the first plated through hole via is associated with a power supply voltage and the second plated through hole via is associated with a ground reference voltage.

10 . The semiconductor package substrate of claim 2 , wherein the plurality of plated through hole vias further comprises:

a first adjacent plated through hole via adjacent and vertically aligned with the first plated through hole via and a second adjacent plated through hole via adjacent and vertically aligned with the second plated through hole via,

wherein the substrate segment separates the first and second adjacent plated through hole vias,

wherein the first adjacent plated through hole via comprises a first adjacent top recess step, and

wherein the second adjacent plated through hole via comprises a second adjacent top recess step; and

an adjacent passive device recess comprising the first adjacent top recess step, an adjacent recess portion in the substrate segment, and the second adjacent top recess step.

11 . The semiconductor package substrate of claim 10 , further comprising a metallization layer comprising a first adjacent contact pad and a second adjacent contact pad, wherein the first adjacent contact pad is positioned overlapping and coupled to a first end portion of an adjacent passive device positioned in the adjacent passive device recess and the second adjacent contact pad is positioned overlapping and coupled to a second end portion of the adjacent passive device positioned in the adjacent passive device recess.

12 . The semiconductor package substrate of claim 10 , further comprising:

a metallization layer comprising a first contact pad and a second contact pad,

wherein the first contact pad is positioned overlapping and coupled to a first end portion of a first top passive device positioned in the top passive device recess and the second contact pad is positioned overlapping and coupled to a second end portion of the first top passive device; and

wherein the first contact pad is positioned overlapping and coupled to a first end portion of a second top passive device positioned in a top adjacent passive device recess and the second contact pad is positioned overlapping and coupled to a second end portion of the second top passive device.

13 . The semiconductor package substrate of claim 10 , wherein the top passive device recess and the adjacent passive device recess are adjoined and form a contiguous recess for a passive device step, and wherein a metallization layer comprises a first contact pad and a second contact pad, wherein the first contact pad is positioned overlapping and coupled to a first end portion of a passive device positioned in the adjoined first top passive device recess and the adjacent passive device recess, and wherein the second contact pad is positioned overlapping and coupled to a second end portion of the passive device.

14 . A semiconductor package comprising:

a semiconductor device positioned over a semiconductor substrate, the semiconductor substrate comprising a core layer with a top and bottom surface and a plurality of plated through hole vias, the plurality of plated through hole vias comprising a first plated through hole via and a second plated through hole via,

wherein the core layer is positioned between a top metallization layer and a bottom metallization layer,

wherein the first plated through hole via comprises a first top recess step,

wherein the second plated through hole via comprises a second top recess step, and

wherein the first plated through hole via further comprises a first bottom recess step and the second plated through hole via further comprises a second bottom recess step;

a substrate segment separating the first and second plated through hole vias;

a top passive device recess comprising the first recess step, the second recess step, and recess portion of the substrate segment, wherein the top passive device recess is positioned in the core layer;

a bottom passive device recess comprising the first bottom recess step, the second bottom recess step, and a bottom recess portion of the substrate segment, wherein the bottom passive device recess is positioned in the core layer; and

a bottom passive device with a first end portion and a second end portion,

wherein the bottom passive device is positioned in the bottom passive device recess; and

an embedded first top passive device with a first end portion and a second end portion, wherein the top passive device is positioned in the top passive device recess, wherein the top passive device is disposed at least partially in the first plated through hole via and the second plated through hole via,

wherein the top passive device recess and the bottom passive device recess are positioned vertically above one another in the core layer.

15 . The semiconductor package of claim 14 further comprising:

a first top contact pad and a second top contact pad in the top metallization layer, wherein the first top contact pad is positioned overlapping and coupled to the first plated through hole via and overlapping and coupled to the first end portion of the top passive device and the second contact pad is positioned overlapping and coupled to the second plated through hole via and overlapping and coupled the second end portion of the top passive device; and

a first bottom contact pad and a second bottom contact pad in the bottom metallization layer, wherein the first bottom contact pad is positioned overlapping and coupled to the first plated through hole via and overlapping and coupled to the first end portion of a bottom passive device and the second bottom contact pad is positioned overlapping and coupled to the second plated through hole via and overlapping and coupled to the second end portion of the bottom passive device.

16 . The semiconductor package of claim 14 , wherein the plurality of plated through hole vias further comprise:

a third plated through hole via spaced apart from the first plated through hole via and the second plated through hole via; and

an embedded second top passive device position between the third plated through hole via and first plated through hole via or the second plated through hole via,

wherein a central axis of the embedded first top passive device and a central axis of the embedded second top passive device are positioned in alignment on a same or adjacent horizontal and/or vertical planes.

17 . A method comprising:

providing a package substrate and forming a plurality of plated through hole vias in the package substrate, the plurality of plated through hole vias comprising a first plated through hole via and a second plated through hole via, wherein the first and second plated through hole vias are separated by a substrate segment;

forming a top passive device recess in a top surface of the package substrate by removing portions of the first plated through hole via to form a first top recess step, the second plated through hole via to form a second top recess step, and the substrate segment to form a top recess portion;

positioning a first end portion of a top passive device in the first top recess step of the first plated through hole via and a second end portion of the top passive device in the second top recess step of the second plated through hole via;

positioning the top passive device in the top passive device recess, wherein the top passive device is disposed at least partially in the first plated through hole via and the second plated through hole via; and

forming a top metallization layer comprising a first top contact pad and a second top contact pad, wherein the first top contact pad overlaps and is coupled to the first plated through hole via and the first end portion of the top passive device, and the second contact pad overlaps and is coupled to the second plated through hole via and the second end portion of the top passive device,

forming a bottom passive device recess in a bottom surface of the package substrate by removing portions of the first plated through hole via to form a first bottom recess step, the second plated through hole via to form a second bottom recess step and the substrate segment to form a bottom recess portion;

positioning a first end portion of a bottom passive device in the first bottom recess step of the first plated through hole via and a second end portion of the bottom passive device in the second recess step of the second plated through hole via; and

forming a bottom metallization layer comprising a first bottom contact pad and a second bottom contact pad, wherein the first bottom contact pad overlaps and is coupled to the first plated through hole via and the first end portion of the bottom passive device, and the second bottom contact pad overlaps and is coupled to the second plated through hole via and the second end portion of the bottom passive device,

wherein the top passive device recess and the bottom passive device recess are positioned vertically above one another in a core layer positioned between the top metallization layer and the bottom metallization layer.