IP Library Granted Patent US 12672559
Granted Patent B2
US 12672559 · App. 17/853,204 · Granted Jun 30, 2026

Low insertion loss coaxial through-hole for highspeed input-ouput

Inventors: Kristof Darmawikarta (Chandler, AZ); Kemal Aygun (Tempe, AZ); Brandon C. Marin (Gilbert, AZ); Srinivas Venkata Ramanuja Pietambaram (Chandler, AZ); Zhiguo Qian (Chandler, AZ); Jiwei Sun (Chandler, AZ)
Assignee: Intel Corporation
H10W70/635H10W20/056H10W42/20H10W44/20H10W70/093H10W70/095H10W70/65H10W44/248H10W90/724
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Quick Facts
Patent No.
US 12672559
App. No.
17/853,204
Granted
Jun 30, 2026
Kind
B2
Abstract

An electronic device includes a substrate including a core layer having a first surface and a second surface opposite the first surface, and at least one coaxial through-hole extending vertically through the core layer from the first surface to the second surface. The coaxial through-hole includes at least a first through-via that includes electrically conductive material extending through the core layer from the first surface to the second surface, and a conductive layer including the same or different electrically conductive material extending vertically through the core layer from the first surface to the second surface and surrounding the first through-via. The conductive layer is to be connected to a ground voltage and is electrically isolated from the first through-via.

Claims (52)

1 . An electronic device, comprising:

a substrate comprising a core layer having a first surface and a second surface opposite the first surface; and

at least one coaxial through-hole extending vertically through the core layer from the first surface to the second surface, wherein the coaxial through-hole comprises:

at least a first through-via that comprises electrically conductive material extending through the core layer from the first surface to the second surface;

a conductive layer comprising the same or a different electrically conductive material and extending vertically through the core layer from the first surface to the second surface, wherein the conductive layer is to be connected to a ground voltage and is electrically isolated from the first through-via;

a second through-via, wherein the conductive layer surrounds the first and second through-vias; and

a first plug material within the conductive layer and surrounding the first and second through-vias, wherein the first plug material has a first dielectric constant, and wherein the first and second through-vias comprise a sidewall of the electrically conductive material and are filled with a second plug material having a second dielectric constant higher than the first dielectric constant.

2 . The electronic device of claim 1 , wherein the first and second through-vias are connected to a differential signal source.

3 . The electronic device of claim 1 , wherein the first plug material comprises at least one of a cyclotene, a benzocyclobutene, a paraffin, or a perfluoroalkyl polymer.

4 . The electronic device of claim 1 , wherein the first plug material comprises an epoxy-based material plugged with at least one of a porous filler, a hollow filler, or a ceramic filler with a dielectric constant less than the second plug material.

5 . The electronic device of claim 1 , comprising a third through-via disposed outside the conductive layer.

6 . The electronic device of claim 5 , wherein the third through-via is connected to the conductive layer and to a ground voltage plane.

7 . The electronic device of claim 1 , comprising:

a first build-up layer contacting the first surface of the core layer, and comprising first bonding pads; and

a second build-up layer contacting the second surface of the core layer and comprising second bonding pads having a different pitch size than the first bonding pads.

8 . A method of forming at least one coaxial through-hole in a core layer of a package substrate, comprising:

forming a first opening in the package substrate;

coating a sidewall of the first opening with an electrically conductive material, thereby forming a conductive layer;

filling the first opening with a first plug material;

forming a second opening in the first plug material with the first plug material surrounding the second opening;

coating a sidewall of the second opening with the same or different electrically conductive material, the sidewall of the second opening having two ends;

filling the second opening with a second plug material that is the same or different than the first plug material;

plating at least one end of the sidewall of the second opening to form a first through-via within the conductive layer that is electrically isolated from the conductive layer;

forming a third opening in the first plug material with the first plug material surrounding the third opening;

coating a sidewall of the third opening with the same or different electrically conductive material, the sidewall of the third opening having two ends;

filling the third opening with the second plug material; and

plating at least one end of the sidewall of the third opening to form a second through-via within the conductive layer.

9 . The method of claim 8 , comprising:

forming a fourth opening in the package substrate;

coating a sidewall of the fourth opening with the same or different electrically conductive material, the sidewall of the fourth opening having two ends;

filling the fourth opening with the second plug material; and

plating at least one end of the sidewall of the fourth opening to form a third through-via outside the conductive layer.

10 . The method of claim 9 , comprising connecting the third through-via to the conductive layer.

11 . The method of claim 8 , comprising:

plating a first surface and a second surface of the first plug material to form a plated first plug material, wherein forming the second and third openings comprises forming the second and third openings in the plated first plug material.

12 . The method of claim 8 , wherein filling the first opening with the first plug material comprises filling the first opening with at least one of a cyclotene, a benzocyclobutene, a paraffin, or a perfluoroalkyl polymer.

13 . The method of claim 8 , wherein filling the first opening with the first plug material comprises filling the first opening with an epoxy-based material plugged with at least one of a porous filler, a hollow filler, or a ceramic filler with a dielectric constant less than the second plug material.

14 . A packaged electronic system, comprising:

a package substrate comprising:

a core layer having a first surface and a second surface opposite the first surface; and

at least one coaxial through-hole extending vertically through the core layer from the first surface to the second surface, wherein the coaxial through-hole comprises:

at least a first through-via that comprises electrically conductive material extending through the core layer from the first surface to the second surface; and

a conductive layer comprising the same or different electrically conductive material extending vertically through the core layer from the first surface to the second surface and surrounding the first through-via, wherein the conductive layer is to be connected to a ground voltage and is electrically isolated from the first through-via; and

a first build-up layer having a bottom surface contacting the first surface of the core layer and an end of the at least one coaxial through-hole;

an integrated circuit (IC) die mounted on a top surface of the first build-up layer, wherein the first build-up layer comprises an electrically conductive interconnect that provides electrical continuity between a bonding pad of the IC die and the at least one coaxial through-hole; and

an antenna operatively coupled to the IC die.

15 . The system of claim 14 , wherein the at least one coaxial through-hole comprises a second through-via that comprises electrically conductive material extending through the core layer from the first surface to the second surface, the first and second through-vias surrounded by the conductive layer, and wherein the first and second through-vias are connected to a differential signal source.

16 . The system of claim 14 , wherein the package substrate comprises a second build-up layer contacting the second surface of the core layer,

wherein the first build-up layer comprises first bonding pads, the second build-up layer comprises second bonding pads, and the second bonding pads have a different pitch size than the first bonding pads.

17 . The system of claim 16 , wherein the second build-up layer comprises an electrically conductive interconnect that provides electrical continuity between the at least one coaxial through-hole and at least one of the second bonding pads.

18 . The system of claim 14 , wherein the at least one coaxial through-hole comprises a second through-via and the conductive layer surrounds the first and second through-vias, and a first plug material within the conductive layer and surrounding the first and second through-vias, wherein the first plug material has a first dielectric constant, and wherein the first and second through-vias comprise a sidewall of the electrically conductive material and are filled with a second plug material having a second dielectric constant higher than the first plug material.

19 . The system of claim 14 , comprising a third through-via outside the conductive layer and connected to the conductive layer and to a ground voltage plane.