IP Library › Granted Patent US 12672572
Granted Patent B2
US 12672572 · App. 17/951,601 · Granted Jun 30, 2026

Package comprising a substrate with interconnects

Inventors: Joan Rey Villarba Buot (Escondido, CA); Hong Bok We (San Diego, CA); Michelle Yejin Kim (Carlsbad, CA); Aniket Patil (San Diego, CA)
Assignee: QUALCOMM INCORPORATED
H10W70/685H10W70/05H10W70/095H10W70/65H10W70/69H10W90/00H10W90/701H10W90/724
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Quick Facts
Patent No.
US 12672572
App. No.
17/951,601
Granted
Jun 30, 2026
Kind
B2
Abstract

A package comprising a substrate and an integrated device coupled to the substrate. The substrate includes a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of interconnects located in the first dielectric layer, the second dielectric layer and the third dielectric layer. The second dielectric layer is located between the first dielectric layer and the third dielectric layer. The second dielectric layer includes a different material than the first dielectric layer and the third dielectric layer.

Claims (119)

1 . A package comprising:

a substrate comprising:

a first dielectric layer;

a second dielectric layer; and

a third dielectric layer,

wherein the second dielectric layer is located between the first dielectric layer and the third dielectric layer,

wherein the second dielectric layer includes a different material than the first dielectric layer and the third dielectric layer,

wherein the second dielectric layer is free of a glass material, and

wherein the first dielectric layer and the third dielectric layer includes a glass material; and

a plurality of interconnects located in the first dielectric layer, the second dielectric layer and the third dielectric layer, wherein the first plurality of interconnects comprise a first column of interconnects and a second column of interconnects, and

an integrated device coupled to the substrate.

2 . The package of claim 1 , wherein the substrate is a coreless substrate that is free of a core layer.

3 . The package of claim 1 , wherein the first dielectric layer and/or the third dielectric layer includes prepreg.

4 . The package of claim 1 ,

wherein the first dielectric layer includes a first thickness, and

wherein the second dielectric layer includes a second thickness that is less than the first thickness.

5 . The package of claim 1 ,

wherein the first column of interconnects comprises:

a first pad interconnect located in the first dielectric layer;

a first via interconnect located in the first dielectric layer, wherein the first via interconnect is coupled to the first pad interconnect;

a second pad interconnect located in the second dielectric layer, wherein the second pad interconnect is coupled to the first via interconnect;

a second via interconnect located in the second dielectric layer, wherein the second via interconnect is coupled to the second pad interconnect;

a third pad interconnect located in the third dielectric layer, wherein the third pad interconnect is coupled to the second via interconnect;

a third via interconnect located in the third dielectric layer, wherein the third via interconnect is coupled to the third pad interconnect; and

a fourth pad interconnect located on a surface of the third dielectric layer, wherein the fourth pad interconnect is coupled to the third pad interconnect,

wherein the second via interconnect has a diameter that is less than a diameter of the first via interconnect and/or a diameter of the third via interconnect, and

wherein the second column of interconnects comprises:

another first pad interconnect located in the first dielectric layer;

another first via interconnect located in the first dielectric layer, wherein the another first via interconnect is coupled to the another first pad interconnect;

another second pad interconnect located in the second dielectric layer, wherein the another second pad interconnect is coupled to the another first via interconnect;

another second via interconnect located in the second dielectric layer, wherein the another second via interconnect is coupled to the another second pad interconnect;

another third pad interconnect located in the third dielectric layer, wherein the another third pad interconnect is coupled to the another second via interconnect;

another third via interconnect located in the third dielectric layer, wherein the another third via interconnect is coupled to the another third pad interconnect; and

another fourth pad interconnect located on a surface of the third dielectric layer, wherein the another fourth pad interconnect is coupled to the another third pad interconnect,

wherein the another second via interconnect has a diameter that is less than a diameter of the another first via interconnect and/or a diameter of the another third via interconnect, and

wherein the first column of interconnects is adjacent to the second column of interconnects.

6 . The package of claim 5 , wherein the integrated device is coupled to the first column of interconnects and the second column of interconnects of the substrate through a plurality of pillar interconnects and a plurality of solder interconnects.

7 . The package of claim 6 , further comprising an integrated passive device coupled to the first column of interconnects and the second column of interconnect of the substrate.

8 . The package of claim 7 ,

wherein the first pad interconnect, the second pad interconnect, the third pad interconnect and the fourth pad interconnect, each comprises a diameter of about 90 micrometers,

wherein the first via interconnect, and the third via interconnect, each comprises a diameter of about 60 micrometers, and

wherein the second via interconnect comprises a diameter of about 50 micrometers.

9 . The package of claim 7 ,

wherein the first column of interconnects is configured to provide a first electrical path between the integrated device and the integrated passive device, and

wherein the second column of interconnects is configured to provide a second electrical path between the integrated device and the integrated passive device.

10 . The package of claim 9 ,

wherein the first column of interconnects is configured to be coupled to power, and

wherein the second column of interconnects is configured to be coupled to ground.

11 . The package of claim 9 ,

wherein a spacing between the first pad interconnect and the another first pad interconnect is the same as a spacing between the second pad interconnect and the another second pad interconnect, and

wherein the spacing between the first pad interconnect and the another first pad interconnect is the same as a spacing between the third pad interconnect and the another third pad interconnect.

12 . The package of claim 1 , wherein the substrate is an embedded trace substrate (ETS).

13 . A substrate comprising:

a first dielectric layer;

a second dielectric layer;

a third dielectric layer,

wherein the second dielectric layer is located between the first dielectric layer and the third dielectric layer,

wherein the second dielectric layer includes a different material than the first dielectric layer and the third dielectric layer;

wherein the second dielectric layer is free of a glass material, and

wherein the first dielectric layer and the third dielectric layer includes a glass material, and

a plurality of interconnects located in the first dielectric layer, the second dielectric layer and the third dielectric layer, wherein the plurality of interconnects comprises a first column of interconnects comprising:

a first pad interconnect located in the first dielectric layer;

a first via interconnect located in the first dielectric layer, wherein the first via interconnect is coupled to the first pad interconnect;

a second pad interconnect located in the second dielectric layer, wherein the second pad interconnect is coupled to the first via interconnect;

a second via interconnect located in the second dielectric layer, wherein the second via interconnect is coupled to the second pad interconnect;

a third pad interconnect located in the third dielectric layer, wherein the third pad interconnect is coupled to the second via interconnect;

a third via interconnect located in the third dielectric layer, wherein the third via interconnect is coupled to the third pad interconnect; and

a fourth pad interconnect located on a surface of the third dielectric layer, wherein the fourth pad interconnect is coupled to the third pad interconnect,

wherein the second via interconnect has a diameter that is less than a diameter of the first via interconnect and/or a diameter of the third via interconnect.

14 . The substrate of claim 13 , wherein the substrate is a coreless substrate that is free of a core layer.

15 . The substrate of claim 13 , wherein the first dielectric layer and/or the third dielectric layer includes prepreg.

16 . The substrate of claim 13 ,

wherein the first dielectric layer includes a first thickness, and

wherein the second dielectric layer includes a second thickness that is less than the first thickness.

17 . The substrate of claim 13 ,

wherein the plurality of interconnects further comprise a second column of interconnects comprising:

another first pad interconnect located in the first dielectric layer;

another first via interconnect located in the first dielectric layer, wherein the another first via interconnect is coupled to the another first pad interconnect;

another second pad interconnect located in the second dielectric layer, wherein the another second pad interconnect is coupled to the another first via interconnect;

another second via interconnect located in the second dielectric layer, wherein the another second via interconnect is coupled to the another second pad interconnect;

another third pad interconnect located in the third dielectric layer, wherein the another third pad interconnect is coupled to the another second via interconnect;

another third via interconnect located in the third dielectric layer, wherein the another third via interconnect is coupled to the another third pad interconnect; and

another fourth pad interconnect located on a surface of the third dielectric layer, wherein the another fourth pad interconnect is coupled to the another third pad interconnect,

wherein the another second via interconnect has a diameter that is less than a diameter of the another first via interconnect and/or a diameter of the another third via interconnect, and

wherein the first column of interconnects is adjacent to the second column of interconnects.

18 . The substrate of claim 17 ,

wherein a spacing between the first pad interconnect and the another first pad interconnect is the same as a spacing between the second pad interconnect and the another second pad interconnect, and

wherein the spacing between the first pad interconnect and the another first pad interconnect is the same as a spacing between the third pad interconnect and the another third pad interconnect.

19 . The substrate of claim 13 , wherein the substrate is a an embedded trace substrate (ETS).

20 . The substrate of claim 13 , wherein the substrate is implemented in a device selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, and a device in an automotive vehicle.

21 . A method for fabricating a package, comprising:

providing a substrate comprising:

a first dielectric layer;

a second dielectric layer;

a third dielectric layer,

wherein the second dielectric layer is located between the first dielectric layer and the third dielectric layer, and

wherein the second dielectric layer includes a different material than the first dielectric layer and the third dielectric layer,

wherein the second dielectric layer is free of a glass material, and

wherein the first dielectric layer and the third dielectric layer includes a glass material; and

a plurality of interconnects located in the first dielectric layer, the second dielectric layer and the third dielectric layer, wherein the plurality of interconnects comprises:

a first column of interconnects comprising:

a first pad interconnect located in the first dielectric layer;

a first via interconnect located in the first dielectric layer, wherein the first via interconnect is coupled to the first pad interconnect;

a second pad interconnect located in the second dielectric layer, wherein the second pad interconnect is coupled to the first via interconnect;

a second via interconnect located in the second dielectric layer, wherein the second via interconnect is coupled to the second pad interconnect;

a third pad interconnect located in the third dielectric layer, wherein the third pad interconnect is coupled to the second via interconnect;

a third via interconnect located in the third dielectric layer, wherein the third via interconnect is coupled to the third pad interconnect; and

a fourth pad interconnect located on a surface of the third dielectric layer,

wherein the fourth pad interconnect is coupled to the third pad interconnect,

wherein the second via interconnect has a diameter that is less than a diameter of the first via interconnect and/or a diameter of the third via interconnect, and

coupling an integrated device to the substrate.

22 . The method of claim 21 , wherein the substrate is a coreless substrate that is free of a core layer.

23 . The method of claim 21 , wherein the first dielectric layer and/or the third dielectric layer includes prepreg.

24 . The method of claim 21 ,

wherein the first dielectric layer includes a first thickness, and

wherein the second dielectric layer includes a second thickness that is less than the first thickness.

25 . The method of claim 24 , wherein the plurality of interconnects comprises:

a first via interconnect located in the first dielectric layer, wherein the first via interconnect comprises a first via thickness; and

a second via interconnect located in the second dielectric layer, wherein the second via interconnect comprises a second via thickness that is less than the first via thickness.