Semiconductor structure and method for arranging redistribution layer of semiconductor device
A semiconductor device is provided, which includes a semiconductor die and a redistribution layer. The redistribution layer is formed on the semiconductor die, and includes a plurality of center pads, a plurality of edge pads, and a plurality of conductive wires electrically connecting the plurality of center pads to the plurality of edge pads. Each of the plurality of conductive wires comprises at least two turning points, and an inner angle at each turning point is greater than a predetermined angle.
1 . A semiconductor structure, comprising:
a substrate, having a first surface and a conductive trace extending above the substrate;
a semiconductor device, disposed on the first surface of the substrate, the semiconductor device comprising:
a semiconductor die; and
a redistribution layer, formed on the semiconductor die, the redistribution layer comprising:
a plurality of center pads;
a plurality of edge pads; and
a plurality of conductive wires, electrically connecting the plurality of center pads to the plurality of edge pads; and
a plurality of bonding wires, electrically connected between the substrate and the plurality of edge pads,
wherein each of the plurality of conductive wires comprises at least two turning points, and an inner angle at each turning point is greater than a predetermined angle;
wherein each of the plurality of conductive wires is turned at a same angular direction at each of the inner angles from one of the center pads to the corresponding edge pad.
2 . The semiconductor structure of claim 1 , wherein the center pads are arranged in a first row and a second row proximate to a center line in a center region of the semiconductor device, and the center line extends along a first direction.
3 . The semiconductor structure of claim 2 , wherein the center pads in the first row and the second row are interleaved, such that the center pads in the first row are not aligned with the center pads in the second row in a second direction which is perpendicular to the first direction.
4 . The semiconductor structure of claim 3 , wherein the edge pads are disposed in a first edge region and a second edge region of the semiconductor device, and the second edge region is opposite to the first edge region.
5 . The semiconductor structure of claim 4 , wherein the edge pads disposed in the first edge region and the second edge region are spaced apart along a second direction, and the second direction is substantially perpendicular to the first direction.
6 . The semiconductor structure of claim 1 , wherein each conductive wire comprises a first segment, a second segment, and a third segment, and the at least two turning points comprise a first turning point and a second turning point,
wherein the first turning point is between the first segment and the second segment, and the second turning point is between the second segment and the third segment.
7 . The semiconductor structure of claim 6 , wherein a first inner angle at the first turning point is substantially equal to a second inner angle at the second turning point.
8 . The semiconductor structure of claim 6 , wherein a first inner angle at the first turning point is different from a second inner angle at the second turning point.
9 . The semiconductor structure of claim 1 , wherein the conductive wires comprises power lines, ground lines, and signal lines, and a first width of the power lines and the ground lines is greater than a second width of the signal lines.
10 . The semiconductor structure of claim 1 , wherein the predetermined angle is between 136 degrees and 179 degrees, wherein the center pads and the edge pads are bump pads and are identical with each other.
11 . The semiconductor structure of claim 4 , wherein the plurality of bonding wires comprises a plurality of first bonding wires and a plurality of second bonding wires, and the plurality of first bonding wires are electrically connected between the edge pads in the first edge region and the substrate, and the plurality of second bonding wires are electrically connected between the edge pads in the second edge region and the substrate.
12 . The semiconductor structure of claim 1 , further comprising a molding compound, disposed above the first surface of the substrate, and covering the semiconductor device.
13 . The semiconductor structure of claim 1 , further comprising a conductive bump disposed on a second surface of the substrate, wherein the second surface is opposite to the first surface.