IP Library Granted Patent US 12672576
Granted Patent B2
US 12672576 · App. 17/735,126 · Granted Jun 30, 2026

Semiconductor structure and manufacturing method thereof

Inventors: Chin-Chia Yang (Tainan City, TW); Da-Jun Lin (Kaohsiung City, TW); Fu-Yu Tsai (Tainan City, TW); Bin-Siang Tsai (Changhua County, TW)
Assignee: United Microelectronics Corp.
H10W72/90H10W99/00H10W80/312H10W80/327H10W90/792
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Quick Facts
Patent No.
US 12672576
App. No.
17/735,126
Granted
Jun 30, 2026
Kind
B2
Abstract

A semiconductor structure including a first substrate, a first dielectric layer, a first oxygen doped carbide (ODC) bonding layer, a second substrate, a second dielectric layer, and a second ODC bonding layer is provided. The first dielectric layer is located on the first substrate. The first ODC bonding layer is located on the first dielectric layer. The second dielectric layer is located on the second substrate. The second ODC bonding layer is located on the second dielectric layer. The first ODC bonding layer and the second ODC bonding layer are bonded to each other.

Claims (29)

1 . A semiconductor structure, comprising:

a first substrate;

a first dielectric layer located on the first substrate;

a first oxygen doped carbide (ODC) bonding layer located on the first dielectric layer;

a second substrate;

a second dielectric layer located on the second substrate;

a second ODC bonding layer located on the second dielectric layer;

a first bonding pad located in the first ODC bonding layer; and

a second bonding pad located in the second ODC bonding layer, wherein

the first ODC bonding layer and the second ODC bonding layer are bonded to each other,

the first dielectric layer comprises a third dielectric layer and a fourth dielectric layer,

the third dielectric layer is located on the substrate,

the fourth dielectric layer is located on third dielectric layer,

a material of the third dielectric layer is nitrogen doped carbide material,

there is an opening in the first ODC bonding layer and the first dielectric layer,

a bottommost surface of the opening is higher than a top surface of the third dielectric layer,

there is an interface between the third dielectric layer and the fourth dielectric layer,

an entire surface of the first bonding pad is aligned with an entire surface of the second bonding pad, and

the first ODC bonding layer, the fourth dielectric layer, and the third dielectric layer are three consecutive layers.

2 . The semiconductor structure according to claim 1 , wherein a material of the first ODC bonding layer comprises silicon oxycarbide.

3 . The semiconductor structure according to claim 1 , wherein a material of the second ODC bonding layer comprises silicon oxycarbide.

4 . The semiconductor structure according to claim 1 , wherein the first bonding pad and the second bonding pad are bonded to each other.

5 . The semiconductor structure according to claim 1 , wherein

the first bonding pad is further located in the first dielectric layer, and

the second bonding pad is further located in the second dielectric layer.

6 . The semiconductor structure according to claim 1 , wherein a material of the first dielectric layer comprises silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, or a combination thereof.

7 . The semiconductor structure according to claim 1 , wherein a material of the second dielectric layer comprises silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, or a combination thereof.

8 . The semiconductor structure according to claim 1 , wherein the first substrate comprises a substrate of a wafer or a substrate of a chip.

9 . The semiconductor structure according to claim 1 , wherein the second substrate comprises a substrate of a wafer or a substrate of a chip.