IP Library Granted Patent US 12672579
Granted Patent B2
US 12672579 · App. 18/390,205 · Granted Jun 30, 2026

Method of fabricating semiconductor package and semiconductor package structure including the semiconductor package

Inventors: Junghyun Roh (Suwon-si, KR); Wangsun Lim (Suwon-si, KR); Manhee Han (Suwon-si, KR); Jaeyoung Hong (Suwon-si, KR)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
H10W74/01H10W72/019H10W72/01951H10W72/0198
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Quick Facts
Patent No.
US 12672579
App. No.
18/390,205
Granted
Jun 30, 2026
Kind
B2
Abstract

Provided is a method of fabricating a semiconductor package, the method including forming a passivation layer and a first protective layer covering a semiconductor substrate and conductive pad above a first surface of the semiconductor substrate, removing a portion of the passivation layer and a portion of the first protective layer to expose the conductive pad, forming a second protective layer covering the conductive pad on the first protective layer, grinding a second surface opposite the first surface of the semiconductor substrate, dicing the semiconductor substrate, and removing the second protective layer to expose the conductive pad, wherein the second protective layer does not expose the conductive pad during the grinding and during the dicing.

Claims (44)

1 . A method of fabricating a semiconductor package, the method comprising:

forming a passivation layer and a first protective layer covering a semiconductor substrate and a conductive pad above a first surface of the semiconductor substrate;

removing a portion of the passivation layer and a portion of the first protective layer to expose the conductive pad;

forming a second protective layer covering the conductive pad on the first protective layer;

grinding a second surface opposite the first surface of the semiconductor substrate;

dicing the semiconductor substrate; and

removing the second protective layer to expose the conductive pad,

wherein the second protective layer does not expose the conductive pad in the grinding process and the dicing process.

2 . The method of claim 1 , wherein the method further comprises performing a hard-baking of the first protective layer after exposing the conductive pad, and

wherein the method does not perform a hard-baking of the second protective layer.

3 . The method of claim 1 , wherein the dicing of the semiconductor substrate is performed using at least one of a blade and a laser.

4 . The method of claim 1 , wherein the first protective layer includes a photosensitive material.

5 . The method of claim 1 , wherein a thickness of the first protective layer is 3 μm or less.

6 . The method of claim 1 , wherein a thickness of the second protective layer is greater than a thickness of the first protective layer.

7 . The method of claim 1 , wherein at least a portion of the first protective layer is not removed while the second protective layer is removed.

8 . A method of fabricating a semiconductor package structure, the method comprising:

forming a first semiconductor package including forming a first protective layer exposing a first conductive pad above a first surface of a first semiconductor substrate, forming a second protective layer covering the first conductive pad on the first protective layer, performing a soft-baking of the second protective layer, and removing the second protective layer to expose the first conductive pad;

forming a second semiconductor package including forming a third protective layer exposing a second conductive pad above a first surface of a second semiconductor substrate, forming a fourth protective layer covering the second conductive pad on the third protective layer, and removing the fourth protective layer to expose the second conductive pad; and

mounting the first semiconductor package on a package substrate and the second semiconductor package on the first semiconductor package.

9 . The method of claim 8 , wherein the method further comprises performing a hard-baking of the first protective layer, and

wherein the method does not perform a hard-baking of the second protective layer.

10 . The method of claim 8 , further comprising:

grinding a second surface opposite the first surface of the first semiconductor substrate; and

dicing the first semiconductor substrate;

wherein the second protective layer does not expose the first conductive pad during the dicing and during the grinding.

11 . The method of claim 10 , wherein the dicing of the first semiconductor substrate is performed using at least one of a blade and a laser.

12 . The method of claim 8 , further comprising electrically connecting the first conductive pad and the second conductive pad to the package substrate.

13 . The method of claim 8 , wherein the first protective layer includes a photosensitive material.

14 . The method of claim 13 , wherein the second protective layer includes a photosensitive material.

15 . The method of claim 8 , wherein a thickness of the second protective layer is greater than a thickness of the first protective layer.

16 . A method of fabricating a semiconductor package, the method comprising:

forming a passivation layer and a first protective layer covering a semiconductor substrate and a conductive pad above a first surface of the semiconductor substrate, the first protective layer including a photosensitive material;

removing a portion of the passivation layer and a portion of the first protective layer to expose the conductive pad;

performing a hard-baking of the first protective layer;

forming a second protective layer covering the conductive pad on the first protective layer;

grinding a second surface opposite the first surface of the semiconductor substrate;

dicing the semiconductor substrate;

removing the second protective layer to expose the conductive pad; and

connecting the exposed conductive pad to a conductive connector;

wherein the second protective layer does not expose the conductive pad in the grinding operation and the dicing operation.

17 . The method of claim 16 , wherein at least a portion of the first protective layer is not removed while the second protective layer is removed.

18 . The method of claim 16 , wherein the second protective layer includes a photosensitive material.

19 . The method of claim 16 , wherein the method does not perform a hard-baking of the second protective layer.

20 . The method of claim 16 , wherein the forming of the second protective layer includes a spin-coating process.