Mesa device with stack thin film passivation
View Patent ↗An overvoltage protection device may include an n-type semiconductor substrate, a p-type layer disposed atop the n-type semiconductor substrate, and a passivation region formed in the n-type semiconductor substrate and the p-type layer, wherein the passivation region comprises a semi-insulating polycrystalline silicon (SIPOS) layer.
1 . An overvoltage protection device, comprising:
an n-type semiconductor substrate;
a p-type layer disposed atop the n-type semiconductor substrate;
a passivation region formed in the n-type semiconductor substrate and the p-type layer, wherein the passivation region comprises a semi-insulating polycrystalline silicon (SIPOS) layer; and
an oxide-nitride-oxide (ONO) layer atop the SIPOS layer, wherein no portion of the ONO layer is formed directly atop a top surface of the p-type layer.
2 . The overvoltage protection device of claim 1 , wherein the SIPOS layer extends partially along the top surface of the p-type layer.
3 . A method of forming an overvoltage protection device, the method comprising:
forming a p-type layer atop an n-type semiconductor substrate;
forming a passivation region in the n-type semiconductor substrate and the p-type layer, wherein the passivation region comprises a semi-insulating polycrystalline silicon (SIPOS) layer; and
forming an oxide-nitride-oxide (ONO) layer atop the SIPOS layer without forming the ONO layer directly atop a top surface of the p-type layer.
4 . The method of claim 3 , further comprising forming the SIPOS layer partially along the top surface of the p-type layer.